diff --git a/cortex-m/CHANGELOG.md b/cortex-m/CHANGELOG.md
index 0c7d273a..941655ce 100644
--- a/cortex-m/CHANGELOG.md
+++ b/cortex-m/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.7.10] - 2026-10-21
+
 ### Removed
 - The separate `#[cfg(not(cortex_m))]` stub for `interrupt::free`.
 
@@ -18,6 +20,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Fix compiler ordering around interrupt-mask writes.
 - `NVIC`'s interrupt-bitmap accessors no longer emit a bounds check and a panic
   path.
+- Add ISB when changing BASEPRI and PRIMASK
 
 ## [v0.7.9] - 2026-08-18
 
@@ -816,7 +819,8 @@ fn main() {
 - Functions to get the vector table
 - Wrappers over miscellaneous instructions like `bkpt`
 
-[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.7.9...HEAD
+[Unreleased]: https://github.com/rust-embedded/cortex-m/compare/v0.7.10...HEAD
+[v0.7.10]: https://github.com/rust-embedded/cortex-m/compare/v0.7.9...v0.7.10
 [v0.7.9]: https://github.com/rust-embedded/cortex-m/compare/v0.7.8...v0.7.9
 [v0.7.8]: https://github.com/rust-embedded/cortex-m/compare/v0.7.7...v0.7.8
 [v0.7.7]: https://github.com/rust-embedded/cortex-m/compare/v0.7.6...v0.7.7
diff --git a/cortex-m/Cargo.toml b/cortex-m/Cargo.toml
index aed49385..832902d5 100644
--- a/cortex-m/Cargo.toml
+++ b/cortex-m/Cargo.toml
@@ -8,7 +8,7 @@ name = "cortex-m"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/cortex-m"
 edition = "2024"
-version = "0.7.9"
+version = "0.7.10"
 links = "cortex-m"  # prevent multiple versions of this crate to be linked together
 rust-version = "1.85"
 
diff --git a/cortex-m/src/register/basepri.rs b/cortex-m/src/register/basepri.rs
index abf8dd34..12be5471 100644
--- a/cortex-m/src/register/basepri.rs
+++ b/cortex-m/src/register/basepri.rs
@@ -30,7 +30,14 @@ pub unsafe fn write(basepri: u8) {
 
     #[cfg(not(feature = "cm7-r0p1"))]
     {
-        unsafe { asm!("msr BASEPRI, {}", in(reg) basepri, options(nostack, preserves_flags)) };
+        unsafe {
+            asm!(
+                "msr BASEPRI, {}",
+                "isb",
+                in(reg) basepri,
+                options(nostack, preserves_flags),
+            )
+        };
     }
 
     #[cfg(feature = "cm7-r0p1")]
@@ -41,6 +48,7 @@ pub unsafe fn write(basepri: u8) {
                 "cpsid i",
                 "tst.w {1}, #1",
                 "msr BASEPRI, {0}",
+                "isb",
                 "it ne",
                 "bxne lr",
                 "cpsie i",
diff --git a/cortex-m/src/register/basepri_max.rs b/cortex-m/src/register/basepri_max.rs
index 2971bdd6..6638ace5 100644
--- a/cortex-m/src/register/basepri_max.rs
+++ b/cortex-m/src/register/basepri_max.rs
@@ -20,7 +20,14 @@ use cortex_m_macros::asm_cfg;
 pub fn write(basepri: u8) {
     #[cfg(not(feature = "cm7-r0p1"))]
     {
-        unsafe { asm!("msr BASEPRI_MAX, {}", in(reg) basepri, options(nostack, preserves_flags)) };
+        unsafe {
+            asm!(
+                "msr BASEPRI_MAX, {}",
+                "isb",
+                in(reg) basepri,
+                options(nostack, preserves_flags)
+            )
+        };
     }
 
     #[cfg(feature = "cm7-r0p1")]
@@ -31,6 +38,7 @@ pub fn write(basepri: u8) {
                 "cpsid i",
                 "tst.w {1}, #1",
                 "msr BASEPRI_MAX, {0}",
+                "isb",
                 "it ne",
                 "bxne lr",
                 "cpsie i",
diff --git a/cortex-m/src/register/primask.rs b/cortex-m/src/register/primask.rs
index 1effa364..6d9b763c 100644
--- a/cortex-m/src/register/primask.rs
+++ b/cortex-m/src/register/primask.rs
@@ -66,7 +66,14 @@ pub fn read_raw() -> u32 {
 pub unsafe fn write_raw(r: u32) {
     // Ensure no preceeding memory accesses are reordered to after interrupts are possibly enabled.
     compiler_fence(Ordering::SeqCst);
-    unsafe { asm!("msr PRIMASK, {}", in(reg) r, options(nostack, preserves_flags)) };
+    unsafe {
+        asm!(
+            "msr PRIMASK, {}",
+            "isb",
+            in(reg) r,
+            options(nostack, preserves_flags),
+        )
+    };
     // Ensure no subsequent memory accesses are reordered to before interrupts are possibly disabled.
     compiler_fence(Ordering::SeqCst);
 }