From 957d67277fdd9eef5a9b369adeb26843895b6771 Mon Sep 17 00:00:00 2001 From: atomchild411 <143453386+atomchild411@users.noreply.github.com> Date: Mon, 19 Oct 2026 19:10:30 -0800 Subject: [PATCH] cpu: mark an exception vector as a compile-worthy arrival jitv2 requests a compile where execution lands on a page's word 0 or after a taken transfer. Exception delivery writes PC straight to the vector, and of the vectors only the 32-bit TLB refill sits on word 0: the XTLB refill (0x080) and the general vector (0x180) were never requested, so TLB faults, syscalls and interrupt entry (and every refill under a kernel running with UX set) ran in the interpreter. A trigger at an entry that is already runnable costs nothing. cpubench, interleaved with main: Indy (R4400) 32 MB miss read +14% (its page faults enter through the general vector), everything else and the IP28 unchanged. Co-Authored-By: Claude Opus 5.5 --- src/cpu/mips_core.rs | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/cpu/mips_core.rs b/src/cpu/mips_core.rs index fd9da1d9a..1de3f4a73 100644 --- a/src/cpu/mips_core.rs +++ b/src/cpu/mips_core.rs @@ -2608,6 +2608,18 @@ pub fn deliver_exception_at(core: &mut MipsCore, status: u32, fault_pc: u64, bd: core.pc = vector_base + offset; + // A vector is a region entry, but only the 32-bit refill vector sits on + // a page's word 0, the one landing a page crossing marks as compile- + // worthy. The XTLB refill (0x080, every refill once UX is set, as on the + // O2) and the general vector (0x180, reached by syscalls only through + // their own trigger) were never requested, so every TLB refill ran in + // the interpreter. Once compiled, a trigger at a runnable entry costs + // nothing: dispatch just runs it. + #[cfg(feature = "jitv2")] + { + core.jit_trigger = true; + } + // Jumping to a handler vector ends any delay slot in progress: the vector's // first instruction is never in one. `bd` was already consumed above (into // Cause.BD / EPC), so clearing here cannot lose information.