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Plan: contiguous fast path for the 16-byte key match (D-KEY16) - #1475

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Oct 11, 2026
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Plan only; no code. Adds .claude/plans/key16-contiguous-match-v1.md and its board rows.

Why. ndarray::simd::ternary_match_strided16_to_mask (behind mask-risc's Pred::MatchFacet16Strided, quack's Cmp::MatchFacet16Strided and dir-sim's subtree) gathers every 16-byte key with two scalar 8-byte loads, even at stride 16, where one U64x8 load already holds four whole keys. The compare after the gather is already a fused XOR_AND ternlog; the gather is the cost.

What the plan does.

  • D-KEY16-1: parity coverage first. The 16-byte kernel is missing from ndarray's simd-masking-parity, so no backend besides the in-crate tests checks it.
  • D-KEY16-2: a probe comparing the current kernel, a contiguous stride-16 path and an AVX-512 gather, at 65,536 and 1M rows, with answers checked identical before timing.
  • D-KEY16-3/4: kernel changes, each gated on a pre-registered threshold from that probe, facade-only, with two disable runs.
  • D-KEY16-5: consumer verification in lance-graph. No consumer source changes; lance-graph-java does not call this kernel.

Rejected, with reason: Rust 1.99's u128-in-vector-register asm! path. One key per xmm instruction is slower than eight 64-bit halves per U64x8; ndarray's 69 asm! sites pass no 128-bit values.

Board: INTEGRATION_PLANS.md and STATUS_BOARD.md rows prepended (line counts grew 3770→3779 and 2449→2462). plan_dids.py passes on the new plan; the supersession index was regenerated last and is unchanged. The second commit renames the series from D-K16 to D-KEY16, because the gate's pattern needs two letters after D-.

The ndarray work (D-KEY16-1..4) needs a session with push access to AdaWorldAPI/ndarray.

🤖 Generated with Claude Code

https://claude.ai/code/session_015JH7YkXs5us6g3tG8NiFfP


Generated by Claude Code

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AdaWorldAPI marked this pull request as ready for review October 11, 2026 08:39
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Comment thread .claude/plans/key16-contiguous-match-v1.md Outdated
ndarray's ternary_match_strided16_to_mask gathers each 16-byte key with
two scalar loads even at stride 16, where one U64x8 load holds four keys.
The plan adds a facade-only stride-16 path and measures an AVX-512 gather
for wider strides, both gated on a probe with pre-registered thresholds.
Parity coverage for the existing kernel comes first: it is missing from
ndarray's simd-masking-parity.

The Rust 1.99 u128-in-vector-register asm! path is recorded as rejected,
with its reason. Consumers (mask-risc, quack, dir-sim) change no code.

Board: INTEGRATION_PLANS and STATUS_BOARD rows prepended. The supersession
index was regenerated last and is unchanged.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_015JH7YkXs5us6g3tG8NiFfP
The gate's pattern needs at least two letters after D-, so D-K16 was
invisible to it (measured: plan_dids.py exit 1 before, 0 after).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_015JH7YkXs5us6g3tG8NiFfP
The kernel's input is &[u8] and the first offset may be 1..15, so building
a &[u64] for U64x8::from_slice is undefined behaviour. W3 now adds a byte
load, U64x8::from_le_bytes, to the facade and every backend, with its own
parity case at offsets 0..63; the probe's arm B uses the same load.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_015JH7YkXs5us6g3tG8NiFfP
@AdaWorldAPI
AdaWorldAPI merged commit 7baa05d into main Oct 11, 2026
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