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docs(plan): Soufflé AST→RAM lowering across 64 thought lifetimes - #1612
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| | D-SRAM-1 | Define a **conceptual bound AST → RAM-like schedule** for pure conjunctive selection, including bag vs set, address seal and negative dependencies | Same canonical answers and read sets on hand-built fixtures; every unsupported operation typed-refused | | ||
| | D-SRAM-2 | Prototype cold optimizer rewrites: SCC/strata, magic-set/aperture propagation, predicate ordering, safe dedup; keep optimizer out of hot path | `optimized == unoptimized == source oracle` for query **and** evidential roots; negative controls must fail when rewrite disabled | | ||
| | D-SRAM-3 | Investigate co-addressed physical selection and coordinate proof; exact R2IL `Program` reproducibility across eligible front ends | P1/P2 agree with scalar reference; P3 always refuses; no foreign-gather or phantom equal-row assumption | | ||
| | D-SRAM-4 | Hook recursive region scheduling to already-authorized d′ driver; compare with Datafrog, then Soufflé | Identical least fixpoint for set workloads, terminated cycles, consistent bag categorization; one thought remains live across many iterations | |
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When D-SRAM-4 is implemented, this directs it into the d′ path, but the current source of truth at .claude/board/STATUS_BOARD.md:140 marks D-RA-4 as “VIOLATION — GATHER. DO NOT BUILD,” and .claude/plans/relalg-v1.md:63-71 defines that driver using the prohibited preimage hop. Waiting for a future gate in line 146 does not correct the target, so this phase should instead point to a replacement co-addressed recursion design under H14c/H14d or remain unresolved rather than calling d′ authorized.
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Fixed in #1618 (f95c72fe): D-SRAM-4 is now OPEN/BLOCKED. It no longer targets d′ and waits for a co-addressed recursion design under H14c/H14d.
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| | --- | --- | --- | | ||
| | D-SRAM-0 | Inventory pinned Soufflé AST/ast2ram/RAM passes; map to D-ASM/D-RA/D-TGA owners and current shipped code; establish source notices | Explicit evidence for every mapped pass; no code imported; list gaps and superseded gather plans | | ||
| | D-SRAM-1 | Define a **conceptual bound AST → RAM-like schedule** for pure conjunctive selection, including bag vs set, address seal and negative dependencies | Same canonical answers and read sets on hand-built fixtures; every unsupported operation typed-refused | | ||
| | D-SRAM-2 | Prototype cold optimizer rewrites: SCC/strata, magic-set/aperture propagation, predicate ordering, safe dedup; keep optimizer out of hot path | `optimized == unoptimized == source oracle` for query **and** evidential roots; negative controls must fail when rewrite disabled | |
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For a correctness-preserving optimizer, disabling SCC/magic-set/reordering/dedup rewrites must still produce the same source-oracle answers; only the optimized plan shape or measured work should change. Requiring the negative controls to fail when a rewrite is disabled contradicts the immediately preceding optimized == unoptimized == source oracle gate and would make a correct unoptimized implementation fail the planned suite. The red controls should instead mutate a semantic guard, or explicitly assert only that the expected optimization is absent.
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Fixed in #1618 (f95c72fe): the gate is split. With a rewrite disabled, answers must still match the oracle and only the expected plan shape disappears. Only disabling a semantic guard may turn a test red.
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Purpose
Plan a Soufflé AST → RAM (Relational Algebra Machine) inspired compiler layer for the existing 64-thought epistemic substrate, without introducing a second production engine. Assimilate the Datalog-compatible semantics of Atomese, MeTTa and Narsese into bound relational operations; reuse Datafrog as the existing semi-naive oracle; lower eligible plans through RelAlg/quack → R2IL → mask-risc.
Key insight: compiler loops and Datalog fixpoint iterations execute within a thought. The 6-bit W field identifies a currently resident speculative thought (0 = givens, 1..63 hypotheses); it does not cap recursion at 64 steps. Compile-time liveness may recycle slots only after semantic consumers finish and versioned receipts survive.
Added
.claude/plans/souffle-ram-64-thought-stack-v1.md: D-SRAM-0..7 staged integration, Soufflé AST/ast2ram/RAM harvest, front-end semantic subset, magic-set and SCC/stratification candidates, physical lowering constraints, thought-liveness scheduling, D-TGA/docs(plan): Git porcelain for epistemic algebra, causal Pickaxe and Lance 13 history #1605 Git integration, performance accounting and explicit stop conditions.docs/research/souffle-ram-64-thought-falsifiers.md: 32 preregistered symbolic oracle/negative-control cases. None has been executed.Existing architecture respected
Thought(t)[T_a[i] : T_b[i]], symbolic logic → mask → masked read → terminal.relalg::Relhandles selections over one row universe, not a shipped complete Datalog compiler. D-RA-2/4 and D-TGA-1/3 remain gating dependencies.Verification
Docs-only PR. Verified that both files exist on the branch. Source references were checked against current repository plans and upstream Soufflé documentation. No compilation, benchmarks, runtime parity or generated tests are claimed.
Suggested review order
No runtime code or upstream source copied. Soufflé UPL-1.0 licensing and origin notice are recorded for future source adaptation.