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Rust 1.99, cpu_guard, unsafe inventory, I8x16/U8x16 parity, SAFETY truth sweep - #348
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…SIGILL The default build is target-cpu=native, so a binary built on one machine and run on another with fewer ISA extensions dies on its first such instruction with no explanation. cpu_guard compares the compiled target features with CPUID/XCR0 from a pre-main hook and exits 132 naming the missing features. Nothing changes at build time; cross-building any tier still works. std's is_x86_feature_detected! short-circuits to true for compiled-in features, so the guard reads CPUID directly. Verified under qemu: a v4 build on Haswell/Skylake-Server/Icelake-Server prints the message; a v3 build on Haswell runs normally; a v3 build on a pre-AVX CPU is documented as not covered (the guard itself is VEX-encoded). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
Channel moves in rust-toolchain.toml, the CI clippy/format/feature jobs and both Dockerfiles. rust-version and the CI MSRV rows stay at 1.98.1 because no 1.99-only API is used, so the floor keeps being tested. The 1.99 delta was confined to test code: missing `# Safety` docs on four mock cblas exports, three manual_contains, and a `use std::f64;` that made `f64::NAN` resolve to the newly deprecated module constant. The cpu_guard probe example moves to as_chunks/+=. Gates on 1.99.0: clippy -D warnings v3/v4 all targets; lib tests v3 2507 and v4 2558 passed; doctests; masking parity native (v3 and host), wasm, wasm-scalar, neon-qemu, nightly; codegen witness avx512/avx2; 1.98.1 floor check. Two crates (blas-tests, cesium) fail clippy identically on 1.98.1 and are untouched. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
.claude/knowledge/unsafe-inventory/ lists every code-level unsafe in src/ (903 fork-added, 398 inherited from upstream ndarray) with its kind, a verdict (IRREDUCIBLE, NEEDS-TF, CONSOLIDATE, SAFE-API, UNSAFE-FN-API, SAFE-CRATE, REMOVABLE), the concrete workaround, SAFETY-comment status and soundness flags. The safe_intrinsic_probe re-run on 1.99.0 matches 1.98.1: value intrinsics need unsafe outside a #[target_feature] fn on x86_64 and aarch64, even at baseline, so 212 blocks first judged removable cannot lose their unsafe on this toolchain. Four out-of-bounds paths reachable from safe code were confirmed at source and are listed first; none is fixed in this commit. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
…ave*) Bit positions were cross-checked against llvm/lib/TargetParser/Host.cpp and all match. Two gating differences are fixed to match LLVM, which is what target-cpu=native consults: Darwin saves AVX-512 state lazily, so XCR0 cannot be trusted there and AVX-512 Macs would have been refused; xsave* features require OS AVX state. Pre-AVX CPUs are documented as out of scope by decision. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
sentinel-qa now starts from the inventory and carries the measured facts that decide verdicts: value intrinsics need a #[target_feature] caller on x86_64 and aarch64 (wasm32 excepted), is_*_feature_detected! short-circuits for compiled-in features, debug_assert! is not a bounds check. amx-savant drops the stale 1.94 environment claim and records the verified 1.99 u128 xmm_reg asm operand and the AMX gating gaps the inventory found. Inventory: nightly rows are unsafe by design and exempt from the SAFETY rule; MKL/OpenBLAS rows are tagged lab-only. Vec::into_parts is recorded as a candidate once the floor moves to 1.99. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
I8x16 gains zero/add/sub/min/max on the AVX-512 polyfill, scalar and nightly arms, and U8x16 (NEON's surface) lands on AVX-512 polyfill, scalar, wasm and nightly, exported with u8x16 from every simd.rs block. add/sub wrap on every arm, as NEON's vaddq_s8 does. A new parity group checks all ten methods against a scalar reference on edge lanes and wrap-around, and passes on native v3/v4, wasm, wasm-scalar, neon-qemu and nightly. The register-level cmp_gt is documented as not the G7 gap (it exists on every arm at native widths and is what the constant predicates use), and NEON's cmp_gt transmutes become stores into a local array with SAFETY comments. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
The default build is target-cpu=native and simd_avx2/simd_avx512 compile for every x86_64 build, so "AVX2 baseline", "the workspace pins x86-64-v3" and "AVX2 is a compile-time property" were no longer true. Thirty-odd comments in simd_avx2.rs, I8x16::saturating_abs (SSSE3 is not in the x86_64 baseline), the AVX2-arm selection note in simd.rs and Fingerprint::as_u8x64's docs now state the real precondition: the feature must be present at run time, and that is the caller's obligation. Comment-only; no code changes. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
It claimed a target_feature(enable = "avx2") annotation on the calling path, which does not exist; simd_avx512.rs compiles for every x86_64 build. Found by sentinel-qa while reviewing the held saturating_abs SSSE3 proposal. Comment-only. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
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Merge Risk: 🔵 Low · up to The toolchain history has an incorrect release date, but no material build or runtime failure remains established. The change is mergeable with that documentation correction. Pre-merge checks |
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The title clearly and concisely summarizes the main changes: the Rust 1.99 update, cpu_guard, unsafe inventory, SIMD parity work, and SAFETY comment updates. |
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ndarray::simd is #[cfg(feature = "std")], so the example failed to build in the --no-default-features test steps (tests/stable, E0432). Same gate the other simd-using examples carry. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
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October 10, 2026 06:34
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Codex review on #348: sse4a, tbm, kl, widekl, sha512, sm3, sm4, avxifma, avxvnniint8, avxneconvert and avxvnniint16 were missing, so a native build using one of them could still SIGILL on an older CPU without the diagnostic. Bit positions and OS-state gating copied from LLVM Host.cpp. A new test pins the feature list rustc 1.99 reports across all x86_64 CPU models. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
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3476-3486: 📐 Maintainability & Code Quality | 🔵 Trivial | 💤 Low valueSurround the table with blank lines.
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- Line 25: Update the Rust 1.99.0 current-stable date in the toolchain history
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.claude/agents/amx-savant.md.claude/agents/sentinel-qa.md.claude/blackboard.md.claude/knowledge/masking-ops-state.md.claude/knowledge/unsafe-inventory/README.md.claude/knowledge/vertical-simd-consumer-contract.md.github/workflows/ci.yamlCLAUDE.mdCargo.tomlDockerfileDockerfile.avx512README-DE.mdREADME.mdcrates/blas-mock-tests/src/lib.rscrates/blas-mock-tests/tests/use-blas.rscrates/simd-masking-parity/src/lib.rsexamples/cpu_guard_probe.rsrust-toolchain.tomlsrc/cpu_guard.rssrc/hpc/fingerprint.rssrc/lib.rssrc/simd.rssrc/simd_avx2.rssrc/simd_avx512.rssrc/simd_neon.rssrc/simd_nightly/mod.rssrc/simd_nightly/w1a_types.rssrc/simd_scalar.rssrc/simd_wasm.rstests/numeric.rstools/safe_intrinsic_probe/Cargo.toml
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rustc -V prints the commit date (2026-09-28); 1.99.0 was released on 2026-10-01. Also add the blank line Markdown needs before the gates table. Both from CodeRabbit's review on #348. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
Operator, 2026-10-10: a SIGILL guard for CPUs older than 15 years may be added later; postponed. The doc comment no longer calls it out of scope, and the blackboard records the open design question (the guard must not be VEX-encoded itself). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
crate::simd selects its AVX2 realization whenever AVX-512 is absent and calls AVX2 intrinsics without a runtime check, so a build compiled without avx2 still SIGILLs on an AVX-only CPU (codex review on #348). Operator decision: check it once at startup, never per call, so dispatch stays compile-time. Measured with a baseline build of cpu_guard_probe under qemu: Nehalem, SandyBridge and IvyBridge exit 132 with the message; Haswell and max run. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh
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Work from the 2026-10-10 session prompt (workstreams A–D), plus a build-CPU guard and an
unsafeinventory.Changes
src/cpu_guard.rs). A pre-main CPUID/XCR0 check for builds that use AVX or later. It runs beforemainand exits with 132 and a message naming the missing CPU features. It does not useis_x86_feature_detected!, because that macro returns true for any feature enabled at compile time. Pre-AVX hosts are out of scope by decision: the guard itself is VEX-encoded.rust-versionfloor stays 1.98.1 (checked clean on 1.98.1). Fixed the lints that are new in 1.99..claude/knowledge/unsafe-inventory/: 1,301 sites, each with a verdict and a workaround. Four out-of-bounds paths reachable from safe code are confirmed but not fixed here.I8x16/U8x16on every arm.I8x16gains zero/add/sub/min/max, and a fullU8x16type is added. add/sub wrap on overflow, as on NEON. A cross-arm parity check, codes 0xF00–0xF32, was disable-verified.cmp_gt. Documented as a lane-vs-lane compare outside the masking-ops family (G7) and noted inmasking-ops-state.md. Its transmute is replaced byvst1q.I8x32::saturating_abs, whose comment claimed atarget_featureannotation that does not exist.Gates (debug 0, tier pinned by config)
Not in this PR
saturating_abssafe through an SSSE3 path is waiting for operator approval. sentinel-qa's verdict is CONDITIONAL: it wants an exhaustive 256-value test and a CI line for a baseline build.🤖 Generated with Claude Code
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