[chenshengxin2026]

Summary

Add PTO VMI implementations for every quant/mHC/MoE *_asc.py module on vmi-impl: 12 quant + 9 mHC + 4 MoE, plus a scalar sqrt-softplus helper. Each counterpart is named *_parallel.py and exposes *_parallel entry points. Existing CUDA/ASC files and public dispatch remain available.

The SIMD bodies use CUDA-style scalar T.Parallel, per-lane accumulators, serial reductions and T.reduce_*. ASC kernel launch, persistent scheduling, DMA, buffer versions, expert padding, SF layouts and inter-core reduction structure are retained. Necessary differences and the complete module-to-test mapping are documented in tests/parallel/README.md.

Notable details include exact division, bit-accurate stochastic rounding, FP4 midpoint handling, packed UE8M0 row/column layouts, RMSNorm Mega SF, SwigLU clamp counters and quantized backward, stable TopK ties, Sinkhorn forward/backward, and MoE auxiliary gradients crossing sequence boundaries. One-dimensional MoE backward uses group_size=1; sequence division remains int32 before explicitly widening GM/UB address coordinates.

Required compiler support

This PR depends on TileLang #36 and PTOAS #1703 + #1705. The latter is stacked on #1703. These are submitted support PRs, not features already merged into the upstream defaults.

Required support	Issues	Support PR
Axis/group reductions and grouped/transposed reads	TileLang #17, #18	#36
Bit operations and packed FP4	#19, #20	#36
Version counters, lane-local state, single-writer points	#21, #22, #24	#36
Precise division, dynamic symbols, branch-local temporaries	#25, #26, #27	#36
Runtime broadcasts, integer atomics, nested serial classification, bounded integer compute inlining	#32, #33, #34, #35	#36
Unknown vecscope memory footprints and missing barriers	PTOAS #1702, #1679	#1703
Shared mixed-width tail masks	PTOAS #1704	#1705

Existing upstream work was checked before implementation: TileLang #11 supplies M2/sequential-loop support for #23 and is included as a dependency in #36. #16 and #28 are already in pto-dev. The separate #31 clear/fill work is not duplicated; these examples initialize with Parallel loops.

Validation

All 110 device cases passed: 44 mHC/core + 26 quantization + 23 remaining operator/compiler features + 17 MoE/batched-SF/atomic cases. All four task-submit jobs exited with code 0. Tested commits: TileLang dec29c2f901e11fe2b82369533611e45274870a9, PTOAS 81d9b3570f46a0b2616d4b00f38011c451409778 (including #1703).

The independent acceptance suite in tests/parallel/ checks CPU PyTorch references against actual Ascend 950 results. Every NPU command is wrapped in task-submit, including auxiliary compiler-feature tests. Tests assert generated VMI source, with the documented exception of the preserved generic SIMT pre-split path.

The environment is CANN 9.3, Python 3.12, torch/torch_npu 2.14 and the support PR revisions above. Mixed FP4/FP8 layout search uses the existing PTO_FLAGS='--vmi-layout-max-frontier-entries=4096 --vmi-layout-max-transitions=1000000' option. These are correctness tests, not performance claims or exhaustive coverage of every specialization.

task-submit --device auto --max-time 3600 --timeout 3700 --run '
  export PTO_FLAGS="--vmi-layout-max-frontier-entries=4096 --vmi-layout-max-transitions=1000000"
  python -m pytest -q -s tests/parallel --tb=short
'

Compiler validation: 230 CPU tests passed (one unrelated CUDA compilation test excluded on the Ascend-only host); PTOAS focused suites passed 25 barrier tests and 17 mask tests. Scoped formatting and git diff --check passed.