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Connections tab: PCIe lanes, CPU or chipset, USB speed and motherboard table - #16

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PrimeBuild-pc merged 5 commits into
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feature/pcie-topology
Oct 12, 2026
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PrimeBuild-pc merged 5 commits into
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feature/pcie-topology

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Read-only diagnostics in Devices & latency: the user moves devices physically and presses Scan again.

PCIe

  • Max and current link for the GPU, NVMe drives and PCIe cards, GPU-Z style (PCIe x16 4.0 @ x16 4.0), read from Windows device properties.
  • Radeon cards sit behind their own PCIe switch, so Windows only sees the internal x16 link: the real link comes from ADLX (amdadlx64.dll, shipped with the driver). Verified on an RX 6950 XT.
  • CPU or chipset from AMD chipset switch IDs and Intel PCH root port IDs (pci.ids).
  • CPU–chipset uplink per chipset and a warning when fast devices behind the chipset add up to more than it carries (theoretical bandwidth, stated in the UI).

USB

  • Negotiated speed per hub port (no administrator rights needed): flags USB 3 devices running at USB 2, mice and keyboards behind hubs, and drives or cameras sharing one external hub.

Motherboard table

  • 183 boards across B450, B550, X570, B650(E), X670(E), B850, X870(E), Z490, B460, Z590, B560, Z690, B660, Z790, B760, Z890, B860, from ASUS, MSI, Gigabyte and ASRock manuals and spec pages; each entry keeps its source URL.
  • Turns a lower generation that matches the slot into the board's limit, names the lane-sharing rule behind a missing x8, and points to faster or CPU-wired M.2 slots.

Badges: green ok, yellow check, red losing performance, grey not readable. Strings in all 6 languages.

To test

  • An NVIDIA GPU idle and under load: does Windows' current link speed update on each scan?
  • A Radeon in an x8 slot or with an M.2 sharing lanes: does ADLX report x8?
  • An Intel 600/700/800 PC: CPU/chipset classification of NVMe drives.

Plan: docs/plans/pcie-topology.md. Build with 0 warnings, 199/199 tests.

…et uplink

Read-only check in Devices & latency. Windows gives max and current link for
end devices; Radeon cards behind their own switch get the real link from ADLX.
CPU or chipset comes from AMD chipset switch IDs and Intel PCH root port IDs.
…ing a hub

Hub IOCTLs (no administrator rights needed) give each port's speed and whether
the device could run at SuperSpeed. NVMe rows show the drive model.
…sharing

Known boards turn a lower generation that matches the slot into the board's
limit, name the rule that takes lanes away and point to faster or CPU-wired
M.2 slots. First entry: MSI MPG X570 Gaming Edge WiFi, from its manual.
B450, B550, X570, B650, B650E, X670, X670E, B850, X870 and X870E boards from
ASUS, MSI, Gigabyte and ASRock, each with its source URL.
Adds Z490, B460, Z590, B560, Z690, B660, Z790, B760, Z890 and B860 boards
(183 in total). A drive running x2 in a slot the board wires x2 is the slot's
limit, shown in yellow with the x4 slots, not as missing lanes.
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@PrimeBuild-pc
PrimeBuild-pc merged commit c9e0424 into main Oct 12, 2026
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PrimeBuild-pc deleted the feature/pcie-topology branch October 12, 2026 21:28
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