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Tatsu Ecosystem

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  1. Identity-Subnet Identity-Subnet Public

    Python 5 3

  2. ChipForge_SN84 ChipForge_SN84 Public

    ChipForge (SN84) introduces the first digital design subnet for decentralized hardware innovation. This subnet enables miners to compete in designing real silicon. Processor development is organize…

    Python 4 3

  3. rvgen rvgen Public

    Pure-Python RISC-V instruction generator with built-in functional coverage, auto-regression, and CI-ready dashboards.

    Python 4 1

  4. Document_Understanding_Subnet Document_Understanding_Subnet Public

    Python 3 4

  5. chipforge_eda_server chipforge_eda_server Public

    EDA server for simulating and validating hardware designs described in Verilog/SystemVerilog, focusing on functionality, performance, area, and power evaluation.

    Python 1

  6. chipforge-mcu chipforge-mcu Public

    Open-source RISC-V processor core with hardware cryptography acceleration, developed through decentralized hardware competitions on Bittensor Subnet 84 (ChipForge).

    SystemVerilog 1

Repositories

Showing 9 of 9 repositories
  • chipforge_eda_server Public

    EDA server for simulating and validating hardware designs described in Verilog/SystemVerilog, focusing on functionality, performance, area, and power evaluation.

    TatsuProject/chipforge_eda_server's past year of commit activity
    Python 1 0 0 0 Updated Sep 21, 2026
  • rvgen Public

    Pure-Python RISC-V instruction generator with built-in functional coverage, auto-regression, and CI-ready dashboards.

    TatsuProject/rvgen's past year of commit activity
    Python 4 Apache-2.0 1 0 0 Updated Jun 14, 2026
  • ChipForge_SN84 Public

    ChipForge (SN84) introduces the first digital design subnet for decentralized hardware innovation. This subnet enables miners to compete in designing real silicon. Processor development is organized into on-chain challenges — spanning AI accelerators, cryptographic modules, mini-GPUs, and other critical components.

    TatsuProject/ChipForge_SN84's past year of commit activity
    Python 4 MIT 3 0 0 Updated May 5, 2026
  • chipforge-mcu Public

    Open-source RISC-V processor core with hardware cryptography acceleration, developed through decentralized hardware competitions on Bittensor Subnet 84 (ChipForge).

    TatsuProject/chipforge-mcu's past year of commit activity
    SystemVerilog 1 0 0 0 Updated Apr 25, 2026
  • coralnpu Public Forked from google-coral/coralnpu

    A machine learning accelerator core designed for energy-efficient AI at the edge.

    TatsuProject/coralnpu's past year of commit activity
    Emacs Lisp 0 Apache-2.0 343 0 0 Updated Feb 19, 2026
  • chipforge-challenges Public

    Hardware Design Challenges for Bittensor Subnet

    TatsuProject/chipforge-challenges's past year of commit activity
    0 0 0 0 Updated Nov 28, 2025
  • Document_Understanding_Subnet Public
    TatsuProject/Document_Understanding_Subnet's past year of commit activity
    Python 3 MIT 4 0 0 Updated Jul 2, 2025
  • document_insights_base_model Public
    TatsuProject/document_insights_base_model's past year of commit activity
    Python 0 0 0 0 Updated Apr 12, 2025
  • Identity-Subnet Public
    TatsuProject/Identity-Subnet's past year of commit activity
    Python 5 MIT 3 0 0 Updated Oct 18, 2024

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