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Review r1 of #1277 at 1a747dbArchitecture. The work sits where it belongs. The pure decision now owns two things: what each register must hold ( On the guest runner, the decision sets no bit, so Size: about +120 lines of production code and about +205 of tests and harness. The records grow by about +80 lines: two new records, and spec-ctrl rewritten to Built/Left/Owed. Evidence: the host CI result is exit 1 with 122 of 123 steps green. The only red is BlockingB1 SuggestionsS1 S2 S3 S4 SEND BACK |
…outs its decision names kernel::mitigation::decide named enhanced IBRS, AMD's always-on IBRS, BHI_DIS_S and the microcode's RDRAND and gather mitigations, and nothing set them: every CPU ran under the IA32_SPEC_CTRL and IA32_MCU_OPT_CTRL firmware left. - Decision::spec_ctrl is the CPU's IA32_SPEC_CTRL while no program that asked runs: IBRS where enhanced IBRS or AMD's IBRS-always-on is named, BHI_DIS_S where it is, every other bit clear. arch::mitigation::apply writes it whole wherever Facts::has_spec_ctrl says the MSR exists (Intel "CPUID Enumeration and Architectural MSRs" Table 3; APM Vol. 3 Fn8000_0008_EBX). - Decision::mcu_opt_ctrl_clears names RNGDS_MITG_DIS and GDS_MITG_DIS where their mitigation is named; apply clears them and keeps the rest. - Enhanced IBRS is enumerated only with CPUID.(07H,0):EDX[26], whose bit it sets: a CPU claiming IBRS_ALL without it says so rather than taking #GP. - The words line gives each register as found and as left, the lines take what is in force from what was read back, and Decision::unapplied names whatever the kernel sets that a register shows off. The metal judge refuses a CPU with any, as it refused only LFENCE's before. - The gds-found-disabled arm sets GDS_MITG_DIS before the kernel's write; gds_found_disabled, a T14 row on the shared-debug boot, holds that every CPU read it set and left it clear. - mitigations_in_a_guest holds a KVM guest's lines and read-backs as the metal row holds a bench's, and prints its words: what the guest runner's CPU shows a guest. IBRS on entry, which RSBA parts without enhanced IBRS are named, and AMD's automatic IBRS (EFER) are recorded, not built. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…code - mitigations_in_a_guest prints each guest CPU's words without signature= and microcode=, which name the host's model, into the public run log (B1). - gds_found_disabled says when a CPU read no IA32_MCU_OPT_CTRL, and names GDS_MITG_LOCK where the arm's write did not take; the record says how to read that red (S3, S4). - apply's arm drops an operand the other implies, and its doc says plainly that any other write that does not take is reported (S1, S2). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…14dd245dd5e8c: the masked guest words, the GDS judge's messages; masked
…code - mitigations_in_a_guest prints each guest CPU's lines, its words without signature= and microcode=, which name the host's model, into the public run log (B1). The verdict lines show what the guest's decision makes of the words once the signature is gone. - gds_found_disabled says when a CPU read no IA32_MCU_OPT_CTRL, and names GDS_MITG_LOCK where the arm's write did not take; the record says how to read that red (S3, S4). - apply's arm drops an operand the other implies, and its doc says plainly that any other write that does not take is reported (S1, S2). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Review r2 of #1277 at 98c605cArchitecture. The architecture is unchanged since r1. Round 2 touches four files (+23/−9): the guest row's print, two judge messages, one doc sentence and one redundant operand. The head merges cleanly onto current main Round 1
Can identifying fields still reach public output?Yes, on a red run, by three routes.
Routes 2 and 3 are older than this PR: #1173 added the artifact, the microcode loader logs the signature, and #1243 added the words line. Neither belongs to this row, so they do not block it. They do mean the owner's masking rule is not met on any red guest run, and the orchestrator has to act:
FindingsNo blocking findings. S1 Evidence
LAND |
Problem
kernel::mitigation::decide(#1243) names, per CPU, enhanced IBRS, AMD's always-on IBRS,BHI_DIS_Sand the microcode's RDRAND/RDSEED and gather mitigations, and nothing set them: every CPU ran under theIA32_SPEC_CTRL(0x48) andIA32_MCU_OPT_CTRL(0x123) firmware left (issues/spec-ctrl-and-gds-stay-as-firmware-left-them.md).What changes
IA32_SPEC_CTRLis written whole at each CPU's bring-up withDecision::spec_ctrl:IBRSwhere enhanced IBRS or AMD's always-on IBRS is named,BHI_DIS_Swhere it is, every other bit clear. That is the value while no program that asked runs; the per-program bits are the next PR's. It is written only whereFacts::has_spec_ctrlsays the MSR exists (Intel "CPUID Enumeration and Architectural MSRs" Table 3; APM Vol. 3 Fn8000_0008_EBX).IA32_MCU_OPT_CTRL's opt-outs are cleared where their microcode mitigation is named (Decision::mcu_opt_ctrl_clears):RNGDS_MITG_DISandGDS_MITG_DIS. The other bits are kept.CPUID.(07H,0):EDX[26], which enumerates the bit it sets. A CPU that claimsIBRS_ALLwithout that bit is reported as lacking the control rather than taking#GP.Decision::unappliednames anything the kernel sets that a register shows off; themitigationsmetal row refuses such a CPU. Before, it refused only LFENCE's bit.gds-found-disabled, a boot arm, setsGDS_MITG_DISbefore the kernel's write.gds_found_disabled, a T14 row on theshared-debugboot, holds that every CPU read it set and left it clear.mitigations_in_a_guestholds a KVM guest's lines and read-backs as the metal row holds a bench's. It prints the guest's lines, its words withoutsignature=andmicrocode=, which would name the host's model in a public log. It runs on x86-64 KVM only: the words are the hypervisor's, and TCG's CPU enumerates none of the controls.IBRS on entry, which the decision names for RSBA parts without enhanced IBRS, and AMD's automatic IBRS (
EFER) are recorded rather than built:issues/no-entry-sets-ibrs-on-a-cpu-with-rsba-and-no-enhanced-ibrs.mdandissues/automatic-ibrs-stays-off-on-an-amd-cpu-that-has-it.md. No proving machine needs either.Checks
Head
98c605c46, rebased onto main302fb3698. Round 2 answers review r1: the masked guest lines (B1), and suggestions S1 to S4. The heads moved once more after the host round:mitigations_in_a_guestnow prints every line (masked as before), so a green run shows the guest's verdicts too; onlytests/toyos.rsdiffers from the heads the host checks ran at.IA32_MCU_OPT_CTRL. The fullcargo run -- --ci hostran at the top of the stack, Every entry from Ring 3 clears branch history where the CPU's decision names it #1279'sc07ac2ef3, which carries this branch: exit 1, 122 of 123 steps green; the red isthe build system, the recorded macOSllvm::testsfailure (issues/the-llvm-environment-test-breaks-git-on-macos.md). Clippy at this head: 26 invocations clean.1a747db24):--ci hostexited 1 with 122 of 123 green; the red is the recorded macOSllvm::testsfailure (issues/the-llvm-environment-test-breaks-git-on-macos.md). The round 2 edits are a harness message, a doc sentence and one redundant operand.testcasesimage on the test kernel both build at the top of the stack.mitigations_verdictrefuses the T14's words withIBRSread clear, and withGDS_MITG_DISread set, even when the lines agree with the misread.IA32_SPEC_CTRLredsthe_benches_words_decide_as_their_vendors_rowsandmitigations_verdict(patch and log in the evidence).mitigations_in_a_guest,shared_debug_members_exit_0), queued. Runs 43151862065 and 43165344560 at earlier heads were cancelled.IBRS_ALLorBHI_CTRL. So its decision sets no bit at bring-up, andspec_ctrlshould read0x0. That is an inference until this run's masked words are in the evidence.Evidence: round 1, https://github.com/ToyOSOrg/evidence/tree/b2652ff9150accb5fd2bdb369edfd78e88fcdb97/r1. Round 2 (host), https://github.com/ToyOSOrg/evidence/tree/53e1770d17f34deea19cb865d3d569cd8c9e55f9/r2. The guest round follows.
Owed on metal (benches down)
Recorded in
issues/spec-ctrl-and-gds-stay-as-firmware-left-them.md:mitigationsrow,metalcaseboot of main, on both benches. On the T14,spec_ctrl=0x1andmcu_opt_ctrlwith bits 0 and 4 clear on every CPU; on the AMD bench,spec_ctrl=0x0;gds_found_disabled,shared-debugboot of main, on the T14, and the same boot with the clear deleted, which must red it;🤖 Generated with Claude Code