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Features/g4 can #19
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Features/g4 can #19
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@@ -103,47 +103,83 @@ const uint32_t analogInputPin[] = { | |
| * @param None | ||
| * @retval None | ||
| */ | ||
| WEAK void SystemClock_Config(void) { | ||
| void SystemClock_Config(void) { | ||
| RCC_OscInitTypeDef RCC_OscInitStruct = {}; | ||
| RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; | ||
| RCC_CRSInitTypeDef CRS_Init = {}; | ||
| RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; | ||
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| /** Configure the main internal regulator output voltage | ||
| */ | ||
| HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); | ||
| /* */ | ||
| HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); | ||
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| /** Initializes the RCC Oscillators according to the specified parameters | ||
| * in the RCC_OscInitTypeDef structure. | ||
| */ | ||
| RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; | ||
| RCC_OscInitStruct.HSIState = RCC_HSI_ON; | ||
| RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; | ||
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| /* See RM[275] for clock tree */ | ||
| RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE; | ||
| RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* Our HSE is 8MHz; we use a MEMS oscillator instead of crystal | ||
| oscillator, hence BYPASS (RM[277]) */ | ||
| RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; | ||
| RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; | ||
| RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; | ||
| RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4; | ||
| RCC_OscInitStruct.PLL.PLLN = 85; | ||
| RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; | ||
| RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4; | ||
| RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; | ||
| RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; /* PLL Source is HSE */ | ||
| RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; /* Prescaler; scales down to 4MHz */ | ||
| RCC_OscInitStruct.PLL.PLLN = 60; /* Multiplier; scales up to 240MHz */ | ||
| RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; /* PLLPCLK = 120MHz */ | ||
| RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; /* PLLQCLK = 120MHz */ | ||
| RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; /* PLLRCLK = 120MHz */ | ||
| if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { | ||
| Error_Handler(); | ||
| } | ||
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| /** Initializes the CPU, AHB and APB buses clocks | ||
| */ | ||
| RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; | ||
| RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; | ||
| RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; | ||
| RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; | ||
| RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; | ||
| RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* SYSCLK = PLLRCLK = 120MHz */ | ||
| RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* AHB = 120MHz */ | ||
| RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* APB1 = AHB = 120MHz */ | ||
| RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* APB2 = AHB = 120MHz */ | ||
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| if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { | ||
| /* Note: from RM[75] stm32g474 is a category 3 device */ | ||
| if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { | ||
| Error_Handler(); | ||
| } | ||
| /** Initializes the peripherals clocks | ||
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| /** Enable the SYSCFG APB clock | ||
| */ | ||
| __HAL_RCC_CRS_CLK_ENABLE(); | ||
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| /** Configures CRS | ||
|
jacobh460 marked this conversation as resolved.
Resolved
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| */ | ||
| CRS_Init.Prescaler = RCC_CRS_SYNC_DIV1; | ||
| CRS_Init.Source = RCC_CRS_SYNC_SOURCE_USB; | ||
| CRS_Init.Polarity = RCC_CRS_SYNC_POLARITY_RISING; | ||
| CRS_Init.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000); | ||
| CRS_Init.ErrorLimitValue = 34; | ||
| CRS_Init.HSI48CalibrationValue = 32; | ||
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| HAL_RCCEx_CRSConfig(&CRS_Init); | ||
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| PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; | ||
| PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; | ||
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Contributor
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. interesting that this works on G4, while HSI48 had issues on H7...
Contributor
Author
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Could this have something to do with the fact that we have CRS disabled on the H7? HSI48 is not precise enough alone to be used for USB
Contributor
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. ah that's almost certainly it - we could consider HSI48 + CRS on the H7 then? Not sure what's actually better, but I assume the same thing is better for both. Anyhow, issue for future PRs. |
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| if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { | ||
| Error_Handler(); | ||
| } | ||
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| /* Peripheral clock enable */ | ||
| __HAL_RCC_USB_CLK_ENABLE(); | ||
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| /* Select FDCAN Clock Source */ | ||
| PeriphClkInit = {0}; | ||
| PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; | ||
| PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; | ||
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| if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { | ||
| Error_Handler(); | ||
| } | ||
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| /* Enable FDCAN Peripheral Clock */ | ||
| __HAL_RCC_FDCAN_CLK_ENABLE(); | ||
| } | ||
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