AArch64: Fixes missing memory operand access value for SWP

[Abhinavmadake]

checklist for this pull request

• I've documented or updated the documentation of every API function and struct this PR changes.
• I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description
SWP reads old value from memory and writes the new one, But BaseSWP in llvm-capstone is missing mayLoad/mayStore
While checking for atomic instructions from #2589 i found that SWP's memory access was missing entirely

Fixes the per-operand access seen in the output for all 16 SWP instructions in arch/AArch64/AArch64GenCSMappingInsnOp.inc and per-instruction access in arch/AArch64/AArch64GenCSMappingInsn.inc.

Added suite/auto-sync/inc_patches/AArch64/03_swp_mem_access.patch following the workflow for patch files

Test plan

Added 4 tests covering 4 of the 16 instructions, for all 4 sizes(b/h/w/x) and all 4 ordering (none/a/al/l)

swp     w0, w1, [x2]
swpalb  w3, w4, [x5]
swplh   w6, w7, [sp]
swpa    x8, x9, [x10]

These tests pass with my fix, while they fail without it

Closing issues
-none