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Unify Chips and Code with a computer journey, guided foundations, and complete logic tools - #47

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@durasj

@durasj durasj commented Nov 2, 2026 •

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Chips and Code now uses one interface across Learn, Tools, and About. Legacy course and simulator routes redirect to their canonical replacements, including saved experiment IDs; the old navigation, theme switch, and page chrome have been removed.

The landing page tells a continuous native-scroll story: a complete laptop separates into its components, the view moves into the processor, and the chip resolves into binary signals. Mobile and reduced-motion views present the same sequence as stills. The original logo and indigo identity remain, with explicit contrast-safe text, controls, signal states, and focus rings.

Learning begins with a signal, then supplied NOT and AND gates before NAND. NAND's relationship to AND and its universality are explained through optional deeper theory. Six circuit construction exercises retain Visual, Code, and Split modes, real HDL parsing/simulation, exhaustive tests, draft recovery, and sequential progress. The reference preserves the current experiment; completed NAND observations also survive a full-theory detour.

All existing Boolean logic material has been adapted into full reading in the same style: functions and canonical representation, gate interfaces/composition, HDL and testing, buses, multi-way routing, and design tradeoffs. The source coverage map records corrections and attribution.

Tools now includes:

  • A modernized Hardware simulator with Monaco, tests, output comparisons, pin inspection, examples, local drafts, sharing, and ZIP export. Saving templates creates a copy; edits during a pending save remain unsaved.
  • A Boolean-function lab for all sixteen two-input functions, editable truth tables, canonical expressions, equivalence, and executable NAND-only HDL.
  • A bus/routing lab covering all nine source contracts with validated word inputs and live selector/output behavior.

The bus lab uses dedicated combinational models; it does not add general HDL bus or clock support. Arithmetic, memory, processor, assembly, and high-level software chapters remain future work because they are not in the existing source material. The optional 48-second film has captions and a transcript. Its master remains silent: the connected Runway Free workspace exposes no speech models, so narration is blocked by the plan; no credits or account settings were changed.

Validation on fe454dd: Svelte check reports zero errors or warnings; Cypress TypeScript checks pass; all 277 unit tests pass (one existing todo); and the production build passes. All 40 browser tests pass, covering navigation and legacy redirects, beginner progression, theory detours, visual/code construction, simulator editing and save races, both new tools, mobile layouts, reduced motion, and accessibility without global contrast exclusions. Desktop and mobile screenshots were visually reviewed.

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Project Deployment Actions Updated
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@durasj durasj changed the title Turn Boolean Logic into the playable Signal Isles Reimagine Chips and Code through computer layers with visual and HDL authoring Nov 2, 2026
@durasj durasj changed the title Reimagine Chips and Code through computer layers with visual and HDL authoring Reimagine Chips and Code as a journey through computer layers Nov 2, 2026
@durasj durasj changed the title Reimagine Chips and Code as a journey through computer layers Build a minimal computer-layer journey with progressive circuit learning Nov 2, 2026
@durasj durasj changed the title Build a minimal computer-layer journey with progressive circuit learning Unify Chips and Code with a computer journey, guided foundations, and complete logic tools Nov 2, 2026
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