perf: inline common memory-zero load offsets

[matthargett]

First of a two-PR interpreter performance stack on next.

The common memory-0 i32.load, i32.load8_u, and i32.load16_s paths currently fetch their static offset from the function operand pool on every dispatch. After normal instruction selection, this embeds a 32-bit offset in the existing 8-byte instruction. Other memories and wider offsets retain the original path. Existing opcode numbers stay fixed; the versioned archive format advances to 07. No unsafe code is added.

Three interleaved Release runs per variant at .utility QoS, with the benchmark thread on efficiency cores:

Device	Cycles/call geomean	Retired instructions	Audio DSP wall time	Scalar convolution	Scalar CRC32
iPhone 12 (A14), 7 cases	−2.0%	−2.0%	−3.5%	−5.5%	−2.6%
iPhone XS Max (A12), 7 cases	−2.6%	−1.9%	−1.9%	−3.4%	−11.7%

xmrsplayer was neutral (+0.3% A14, +0.2% A12). A broader load-and-store variant regressed A14 wall time, so stores are excluded here.

Validation: full tinywasm tests with nightly-tail-calls; focused optimized/unoptimized, multi-memory, and memory64/wide-offset tests; no-std parser/validate/archive check; formatting and library Clippy with warnings denied.

[explodingcamera]

Thanks for the PR! The idea seems sound, but the extra pass doesn’t fit the single-pass lowering approach I want to keep. Moving the rewrite into instruction selection could also prevent later load fusions though. I’m planning to add accumulator registers soon, so I’d rather revisit this alongside that work. The second part seems interesting though, I'll have to try that one out once it's ready 👍 There should also be space for a u16 memory index in the instruction too so I'd add that as well together with the registers.