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[sram] assertion for capability write tags being the same on both beats

Status: Open.

#717 In lowRISC/mocha;

· tchilikov-semify opened on Sep 9, 2026

[sram] bring the RAM configuration ports out to the axi_sram boundary

Status: Open.

#715 In lowRISC/mocha;

· tchilikov-semify opened on Sep 8, 2026

[entropy_src] Add missing ASSERT_KNOWN assertions for output signals

Status: Open.

#713 In lowRISC/mocha;

· tchilikov-semify opened on Sep 8, 2026

[gpio] Add missing ASSERT_KNOWN assertions for output signals

Status: Open.

#711 In lowRISC/mocha;

· tchilikov-semify opened on Sep 8, 2026

[clkmgr] update clockmanager documentation for Mocha

Status: Open.

#709 In lowRISC/mocha;

· tchilikov-semify opened on Sep 8, 2026

[i2c] Add missing ASSERT_KNOWN assertions for output signals

Status: Open.

#708 In lowRISC/mocha;

· tchilikov-semify opened on Sep 8, 2026

[kmac] Add missing ASSERT_KNOWN assertions for output signals

Status: Open.

#707 In lowRISC/mocha;

· tchilikov-semify opened on Sep 8, 2026

Import cmdgen from OpenTitan

Status: Open.

#706 In lowRISC/mocha;

· marnovandermaas opened on Sep 8, 2026

[dv,sram] add metrics for each item in the axi_sram.sv vPlan

Status: Open.

#696 In lowRISC/mocha;

· tchilikov-semify opened on Aug 14, 2026

[sram] atomic accesses to axi_sram should return an error

Status: Open.

#695 In lowRISC/mocha;

· tchilikov-semify opened on Aug 3, 2026

prim_ram_1p.sv can behave inconsistently for synthesis/simulation

Status: Open.

#694 In lowRISC/mocha;

· thomas6785 opened on Jul 30, 2026

[sw,dv] %c format specifier not supported by SW-DV log

Status: Open.

#690 In lowRISC/mocha;

· martin-velay opened on Jul 24, 2026