[ainyan03]

Updates the FPGA bitstream used by Module Display / Atom Display (Panel_M5HDMI_FS.h) to the Veryl port of the design: https://github.com/ciniml/atom_display_fpga (feature/veryl-port, 93d419c, GOWIN EDA 1.9.12).

Fixes compared with the bitstream bundled so far:

• COPYRECT no longer hangs busy for a short horizontal shift of an overlapping area.
• A host that pauses in the middle of a pixel stream no longer shifts the picture.
• The stream writer no longer stays busy when the last pixel of a transfer (e.g. a 1 px wide pushImage) arrives while the previous write address is still waiting.

The command protocol is unchanged, so the driver is not touched. The compressed image grows from 227,317 to 247,517 bytes.

Tested on ESP32-P4 + Module Display:

• Randomized drawing load (fillRect / pixels / lines / text / pushImage with and without DMA and transparency / copyRect / alpha) over 640x360, 1280x720, 960x540 on 1080p30 and 1080p60, 320x240 x2, at 8 / 16 / 24 bpp and all rotations: 10 minutes of looping plus one pass each of the plain, mixed and alpha sets, no hang.
• Overlapping copyRect in 8 directions with 16 px and 1 px shifts at 8 / 16 / 24 bpp, compared pixel by pixel against the expected image on an HDMI capture: all match.
• 1920x1080 60 Hz output (148.5 MHz, half clock in the FPGA) captured correctly.

Local build check across the upstream CI versions passed. Fork CI passed.