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Release 0.2.26 - #400
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Release 0.2.26#400
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… it does not block the charger TS has no battery thermistor on these boards; it senses the 5V bus (CoreS3) or reads about 2.9V (Core2 v1.1). REG 0x50 bit 4 selects whether TS qualifies charging, and its power-on default comes from the EFUSE and differs between chips: on units where it is 0, the charger treats the TS voltage as a cold battery and never charges (m5stack#387). Setting the bit is a no-op on chips whose default is already 1.
The charger's CHG_PROG pin (IOE1 G1) switches between 180 mA and 650 mA, the same two steps as CoreMatrix. The code assumed 830 mA for the high step, so setChargeCurrent() with a request between 650 and 829 mA picked 180 mA, and the applied current was reported as 830 mA.
… Core2 v1.1) The power-on value of REG 0x64 (constant-voltage target) is not always the datasheet default (011b = 4.2V): a CoreS3 SE was reported with 0x64 = 0x00, which is reserved in the current datasheet and was listed as 4.6V in an early revision. The cells on these boards are 4.2V types, so the target is now set explicitly at init, before the TS pin setting that lets the charger start. Chips that already read 0x03 are unaffected. A failed write is logged as a warning. A second Power.begin() call sets 4.2V again (when the write succeeds), replacing a lower target set with setChargeVoltage() before it.
On a weak USB supply (several hub levels deep, no battery) the CoreS3 family powered itself off right after begin(): connecting the empty BUS_OUT capacitance through BUS_OUT_EN in setExtOutput(true) pulled the AXP2101 DCDC under its threshold and the PMIC shut down (REG21 = 0x20). Plugging USB in never booted the board; the power key did, because the charge left on BUS_OUT by the failed attempt remained. When BUS_OUT_EN goes from 0 to 1, pulse it first with a growing on-time: each pulse is one 100 kHz register write plus i * 16 us, 1 ms apart, 8 times (about 10 ms). BUS_OUT has a constant discharge path, so short fixed pulses do not accumulate; once it passes about 1.7 V it is pulled up from VBUS even with BUS_OUT_EN = 0 and the final enable is a small step. Measured on a CoreS3 SE, the point is crossed at the 3rd pulse. A write that fails during the ramp is followed by rewriting and reading back BUS_OUT_EN = 0 (up to three times): confirmed off returns false (after a failed on-pulse) or continues the ramp, still on goes to the final enable, unreadable returns false. The final enable is read back and retried, because a precharged BUS_OUT left with BUS_OUT_EN = 0 is pulled up from VBUS and then keeps later setExtOutput(true) calls cancelled by the TS check. The ramp runs only on the 0 -> 1 transition, inside the existing AW9523 lock.
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Fixes
TSpin as a charger input, the battery never charged (the unconnectedTSreads as a cold battery).TSis now set as an external input. (CoreS3: AXP2101 TS pin is used as ADC input but left in battery-temperature mode #387, AXP2101: set the TS pin to external input on CoreS3 and Core2 v1.1 so it does not block the charger #388)M5.Lednever lit; the RGB LED supply switch (NanoC6 GPIO19, NanoH2 GPIO10) was not turned on. It is switched on at the first LED access and off byrelease(). (NanoC6 / NanoH2: switch the RGB LED power on when the LEDs are first used #389)begin()now sets 4.2 V explicitly. (CoreS3: AXP2101 TS pin is used as ADC input but left in battery-temperature mode #387, Power: set the AXP2101 charge voltage to 4.2V at init (CoreS3 family, Core2 v1.1) #392)setExtOutput(true)precharges the 5 V bus with short pulses before enabling it, so that the inrush into the empty bus does not power the board off on a weak USB supply with no battery. (CoreS3 / Core2 v1.1: keep the PMIC on when the 5 V output comes up on a weak USB supply #381)setChargeCurrent()selected the high charge step as 830 mA; the hardware step is 650 mA, so requests of 650 to 829 mA chose 180 mA instead. (ToughC5: select 650 mA, not 830 mA, as the high charge current step #395)