Repository navigation
Sync master (0.2.26) into develop - #401
Merged
Merged
Conversation
… it does not block the charger TS has no battery thermistor on these boards; it senses the 5V bus (CoreS3) or reads about 2.9V (Core2 v1.1). REG 0x50 bit 4 selects whether TS qualifies charging, and its power-on default comes from the EFUSE and differs between chips: on units where it is 0, the charger treats the TS voltage as a cold battery and never charges (m5stack#387). Setting the bit is a no-op on chips whose default is already 1.
The charger's CHG_PROG pin (IOE1 G1) switches between 180 mA and 650 mA, the same two steps as CoreMatrix. The code assumed 830 mA for the high step, so setChargeCurrent() with a request between 650 and 829 mA picked 180 mA, and the applied current was reported as 830 mA.
… Core2 v1.1) The power-on value of REG 0x64 (constant-voltage target) is not always the datasheet default (011b = 4.2V): a CoreS3 SE was reported with 0x64 = 0x00, which is reserved in the current datasheet and was listed as 4.6V in an early revision. The cells on these boards are 4.2V types, so the target is now set explicitly at init, before the TS pin setting that lets the charger start. Chips that already read 0x03 are unaffected. A failed write is logged as a warning. A second Power.begin() call sets 4.2V again (when the write succeeds), replacing a lower target set with setChargeVoltage() before it.
On a weak USB supply (several hub levels deep, no battery) the CoreS3 family powered itself off right after begin(): connecting the empty BUS_OUT capacitance through BUS_OUT_EN in setExtOutput(true) pulled the AXP2101 DCDC under its threshold and the PMIC shut down (REG21 = 0x20). Plugging USB in never booted the board; the power key did, because the charge left on BUS_OUT by the failed attempt remained. When BUS_OUT_EN goes from 0 to 1, pulse it first with a growing on-time: each pulse is one 100 kHz register write plus i * 16 us, 1 ms apart, 8 times (about 10 ms). BUS_OUT has a constant discharge path, so short fixed pulses do not accumulate; once it passes about 1.7 V it is pulled up from VBUS even with BUS_OUT_EN = 0 and the final enable is a small step. Measured on a CoreS3 SE, the point is crossed at the 3rd pulse. A write that fails during the ramp is followed by rewriting and reading back BUS_OUT_EN = 0 (up to three times): confirmed off returns false (after a failed on-pulse) or continues the ramp, still on goes to the final enable, unreadable returns false. The final enable is read back and retried, because a precharged BUS_OUT left with BUS_OUT_EN = 0 is pulled up from VBUS and then keeps later setExtOutput(true) calls cancelled by the TS check. The ramp runs only on the 0 -> 1 transition, inside the existing AW9523 lock.
Release 0.2.26
# Conflicts: # src/M5Unified.inl # src/utility/Power_Class.hpp # src/utility/Power_Class.inl
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Merges the 0.2.26 release (master) back into develop. Conflicts were resolved on the develop side; the only net change against develop is the version bump (4 files). Please merge with "Create a merge commit" (not squash / rebase) so that master stays an ancestor of develop.