RFC-0036: Zero-GC 64-Byte Cache-Aligned Flat Arena (Aventine Labs LLC) - #110
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Signed-off-by: Mark Gilbert (@markbgilbert) <mbgilbert@gmail.com> Co-authored-by: Aventine Systems Engineering <contact@aventinelabs.com>
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Update: Dual-OS 60-Minute Training Soak Receipts (Windows 11 vs. Ubuntu 24.04 LTS) & 92/100 Hardware Verification ScorecardTo address enterprise reviewer feedback regarding multi-hour stability and POSIX kernel performance, we have updated RFC-0036 with physical empirical telemetry from continuous 60-minute training runs on physical hardware (AMD Ryzen 9 9955HX Zen 5 + NVIDIA GeForce RTX 5060 Laptop GPU):
Full reproducible code, raw CSV time-series, and standalone C kernels are available in the public benchmark repository: https://github.com/markbgilbert/aegis-zero-gc-benchmark |
…S matrix, and Meta 95/100 scorecard
… to 92/100 with resolved roadmap
RFC-0036: Zero-GC 64-Byte Cache-Aligned Flat Arena Runtime
Target: Meta AI Infra / FAIR / PyTorch Core / Llama Runtime Teams
Author: Mark Gilbert (@markbgilbert · mbgilbert@gmail.com), Founder & Principal Architect, Aventine Labs LLC
Repository: https://github.com/markbgilbert/aegis-zero-gc-benchmark
Physical Hardware: AMD Ryzen 9 9955HX (Zen 5, 16C/32T) | NVIDIA GeForce RTX 5060 Laptop GPU (8GB GDDR6, Blackwell
sm_120)1. Motivation
High-throughput LLM training and speculative decoding pipelines are increasingly choked not by GPU matrix multiplication, but by host-side memory allocations, dynamic tensor slicing, Python garbage collection jitter, and un-audited telemetry logging.
During speculative decoding tree verification and batch token ingestion, pointer-chasing and dynamic heap allocations cause host CPU stalls, forcing accelerators to idle while waiting for candidate tokens.
This RFC proposes integrating a Zero-GC 64-Byte Cache-Aligned Flat Arena Runtime into PyTorch host-side token ingestion and speculative tree verification to eliminate host jitter and saturate hardware line rates.
2. Empirical Proof: From Prototype to Native Silicon (1-Billion Operation Benchmark)
To establish the hardware ceiling of zero-GC 64-byte aligned flat arenas, we evaluated 1 Billion continuous operations across both managed and compiled environments on physical silicon:
-O3 -mavx2)QueueOrder64)3. Real-World AI Validation: Micro-GPT Feeder Acceleration (Physical Blackwell RTX 5060)
Beyond synthetic loops, we translated Karpathy's
nanoGPTingestion into the native 64-byte flat arena feeder (aegis_feeder.dll/torch.ops.aegis.extract_batch) evaluated on a 10.69M parameter Micro-GPT (6 layers, 6 heads, 384 dim, 256 context):4.2872and converged identically to loss2.5012at Step 50.4. 60-Minute Dual-OS Enterprise Soak Receipts (Windows 11 vs. Ubuntu 24.04 LTS)
To disprove unmanaged heap leaks and isolate OS driver quantization noise from application stability, we executed sustained 1-hour stress tests across both operating systems:
VmRSS)ptmalloc2thread sub-arena allocations5. Proposed PyTorch Integration Points
Rather than attempting to replace the internal CUDA caching allocator in Inductor, this RFC proposes two surgical host integration points:
torch.utils.data.FlatArenaDataLoader:torch.stackand dynamic list slicing with a pre-pinned, 64-byte cache-aligned C ring buffer.alignas(64)), enabling branchless AVX-512 SIMD mask queries for page eviction and reuse.6. Peer Reproduction & Verification
All benchmarks are 100% peer-reproducible using standalone Clang kernels, CMake targets, and raw CSV telemetry logs:
artifacts/aegis_rfc_fair_pytorch.mdin repository