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Add the necessary board widgets, kcontrols and DAPM routes for max98091 codec support. Enable required DAI format, sysclk and other required configs. Signed-off-by: Karthik S <karthik.s@oss.qualcomm.com>
Add the LPASS LPI pinctrl driver for the QCS615 SoC. The driver supports 32 GPIOs in the range 0-31 and provides pin control functionality for the LPASS LPI block. Signed-off-by: Karthik S <karthik.s@oss.qualcomm.com>
The SDCA class driver is useful on non-ACPI platforms where the topology is supplied statically via sdca_class_ops.populate_function. Drop 'depends on ACPI' from SND_SOC_SDCA and guard the ACPI-parsing implementations in sdca_device.c and sdca_functions.c with IS_ENABLED(CONFIG_ACPI), providing empty stubs when ACPI is off. Link: https://lore.kernel.org/all/20260915165652.914893-2-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
The class PM callbacks pull sdca_class_drv out of drvdata, so the built-in class_sdw_driver owns the drvdata slot. That works for the generic case but blocks codec drivers that want to embed sdca_class_drv in their own private struct, they need drvdata for their codec priv. Split the four callbacks into exported helpers that take a struct sdca_class_drv * directly: sdca_class_system_suspend() sdca_class_system_resume() sdca_class_runtime_suspend() sdca_class_runtime_resume() Codec drivers can now compose these into their own dev_pm_ops without going through drvdata. For the built-in class_sdw_driver, add small dev_pm_ops wrappers that fetch drv from drvdata and wire them into sdca_class_pm_ops (kept static; the built-in slave is the only user). No functional change: the built-in class_sdw_driver keeps the same PM semantics; only the internal plumbing shifts to operate on sdca_class_drv instead of struct device *dev. Link: https://lore.kernel.org/all/20260915165652.914893-3-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Split the internal class_sdw_probe/class_sdw_remove functions into caller-friendly library helpers: sdca_class_probe(sdw, drv) sdca_class_remove(drv) The class_sdw_probe/class_sdw_remove callbacks of the built-in class_sdw_driver are now thin wrappers that allocate a bare sdca_class_drv, stash it in drvdata, and defer to the exported helpers. The exported sdca_class_probe() takes a caller-owned struct sdca_class_drv * so codec-specific SoundWire drivers can embed the class state in their own priv struct, own dev_set_drvdata() themselves, and avoid a second allocation. No functional change for the built-in driver. This lays the groundwork for codec-specific SDCA SoundWire drivers that want to compose the class-side probe with their own quirks; the next patches add the class_ops mechanism on top. Link: https://lore.kernel.org/all/20260915165652.914893-4-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Add struct sdca_class_ops with a populate_function callback that lets codec drivers supply the SDCA topology (entities, clusters, init_table, ...) from static tables in place of sdca_parse_function() on DT/non-DisCo platforms. The callback is a pure data source and performs no bus I/O. Codec drivers embed sdca_class_drv in their own priv and register their populate_function through class_ops passed to sdca_class_probe(). Link: https://lore.kernel.org/all/20260915165652.914893-5-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
…index sdca_asoc_populate_dais() sets each DAI id from the SDCA Function's entity array index. ASoC's default of_xlate_dai_name treats the phandle cell as a positional index into the DAI list, so on a Function with non-DAI entries between dataport entities a sound-dai phandle resolves to the wrong DAI. Register a custom of_xlate_dai_name that walks the entity array and returns the dataport entity whose array index matches the cell value. Link: https://lore.kernel.org/all/20260915165652.914893-6-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
…lper sdca_parse_function() derives is_volatile (see c7b6c6b) and the spec-defined reset value (see 02d851b) from each Control's (entity type, selector, access mode). Codecs that ship static SDCA tables via populate_function skip that path, so RW1S action Controls end up with is_volatile=0 and get replayed on every regcache_sync. Add sdca_apply_default_control_classifiers() to re-run those two classifiers over a Function. Link: https://lore.kernel.org/all/20260915165652.914893-7-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Describe the WCD9378 SoundWire peripheral which is SDCA compatible soundwire device. It provides SDCA SimpleJack for headphone playback headset mic capture and MBHC jack detection. The same silicon is integrated in two ways and enumerates with the same SoundWire class ID: mobile mode: two slaves (tx, rx) on separate SoundWire masters. SDCA / compute mode: one aggregated slave on a multi-lane master. Note: both of them have different bus toplogies 1 device vs 2 devices. Currently only compute mode is supported by this bindings, mobile mode will extend this binding as required. Link: https://lore.kernel.org/all/20260915165652.914893-8-srinivas.kandagatla@oss.qualcomm.com/ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Add support for the Qualcomm Tambora (WCD9378) headset codec in SDCA
mode over SoundWire. On ARM/DT platforms without ACPI/DisCo firmware
the SDCA topology and SoundWire port properties are supplied as static
data through the codec driver.
The codec exposes a single SimpleJack SDCA Function providing:
- Headphone playback via FU 6 (mute + Q7.8 volume) and OT 43/45.
- Headset mic capture via IT 33 with MICB2 fixed at 2.75 V (SDCA
MIC_BIAS index 0x5) via the static init_table.
- MBHC-based headset jack detection (not wired up in this series).
Implements:
- sdw_slave_ops.read_prop: SoundWire slave properties and dpn caps
for the compute-mode dataports. Supplies, reset GPIO, and the
vendor TX PDM clock are set up directly in the SoundWire probe.
- sdca_class_ops.populate_function: fills the SDCA Function data
(entities, clusters, init_table) from static tables.
Binds SoundWire slave id 0x0217:0x0110 when the qcom,wcd9378c
variant compatible is set on the DT node.
Link: https://lore.kernel.org/all/20260915165652.914893-9-srinivas.kandagatla@oss.qualcomm.com/
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
mohsRafi
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Dev Completion validation failed CR: 4685816 The change task for this CR could not be moved to Dev Complete because of the error above. Please resolve the issue in Orbit and re-run the failed Orbit check. |
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…tion Address several issues in the SDCA class framework and add support for codec-specific SDCA SoundWire drivers. Changes include: - Fix race between class_boot_work() and sdw_bus_probe() by waiting for SoundWire probe completion before IRQ allocation. - Re-enable IRQs when pm_runtime_force_suspend() fails. - Cancel deferred boot work through devres to avoid use-after-free issues during probe unwind. - Correct pm_runtime reference handling during probe. - Export sdca_class_read_prop() for reuse by codec-specific drivers. - Add sdca_class_hw_ops with hw_init() support. - Add populate_function() callback support for DT-based SDCA devices. - Export sdca_class_pm_ops for codec driver integration. - Allow per-port BPS configuration by deferring BPS selection to compute_params() implementations. These changes improve probe reliability, runtime PM handling and enable integration of codec-specific SDCA implementations such as WCD9378-SDCA. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
…ing updates Add device tree binding updates required for Glymur audio support and recent Qualcomm SoundWire enhancements. This change introduces bindings for the Glymur LPASS clock controller along with the associated clock ID definitions used by LPASS macro codecs and SoundWire controllers. It also updates the Qualcomm SoundWire bindings to: - Allow vendor-specific compatibles alongside SoundWire class-ID compatibles on slave devices. - Document the qcom,ports-ch-mask property used for per-port channel mask configuration. - Describe SoundWire lane provider and consumer topologies for platforms that combine multiple controller instances to expose additional data lanes. These updates align the DT schemas with existing driver functionality and provide the bindings required for upcoming Glymur audio platform support. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
…pport Add the SoundWire core and Qualcomm controller changes required for SDCA codec topologies and for Qualcomm SoCs that combine two controller instances to expose additional data lanes. Core stream changes: - Allow a Slave to contribute more than one port to the same stream across multiple sdw_stream_add_slave() calls. Ports are now always appended to port_list and the pre-call count is used so port configuration only fills in newly added entries instead of overwriting those from earlier calls. - Preserve per-port port_params.bps pre-set by compute_params() and only fall back to the stream-wide value when it was left at zero, so a single stream can carry ports with different wire widths. - Explicitly set port_params.num so master port_params callbacks always receive the correct port number. Qualcomm controller changes: - Add the optional qcom,ports-ch-mask property to fix the per-port channel mask where the stream derived value is insufficient, such as a wired stereo PDM port opened by a mono PCM stream. - Gate the additional DIN PCM port control register for ports that belong to a PCM stream, as required by SDCA class compliant slaves. - Implement the lane provider role, where a controller declaring #qcom,swrm-lane-cells is brought up as a data only lane source and does not register a SoundWire bus of its own. - Implement the lane consumer role, where qcom,secondary-lanes resolves a provider at probe time and deferred probe is used until the provider is ready. Per-port DPn register accesses that land on a borrowed lane are translated and routed to the provider, and the port lane selector is converted to provider local numbering. - Program MM_SYNC on both controllers of a multi-master pair so their frame generators lock to a single SWR_CLK, and re-apply it on resume since it does not survive a bus clock stop. - Program the frame control SSP period derived from the current frame geometry on v3.1.0+ parts, both at init and on every bank switch, and clear CLK_DIV in the same place. - Fan broadcast SCP_FrameCtrl writes out to per-slave unicasts on a multi-master pair, where the hardware broadcast is not acted upon by the slaves. Bus changes: - Iterate every string in a slave node compatible property when matching the SoundWire class ID, so a vendor variant compatible can precede the class ID compatible. Non-multilane platforms are unaffected: without qcom,secondary-lanes no provider is resolved and all register accesses keep using the existing paths. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
…ister cache handling Add LPASS macro codec support for codec version 2.9 and correct several register cache issues affecting all four macro codecs. Codec version handling in lpass-rx-macro: - Handle LPASS_CODEC_VERSION_2_9 in the version based switch statements so it is treated the same as the other members of the 2.5 family, which is what Glymur requires. This covers the read-write register check, the control and widget selection at component probe, and the register stride and default table selection at probe. - Add LPASS_MACRO_FLAG_HAS_NPL_CLOCK to the sm8550 match entry. The missing flag left sm8550 running without its NPL clock, which caused sporadic playback stalls. Register default sorting in lpass-rx-macro and lpass-wsa-macro: - Both drivers build the register defaults array by concatenating a base table with a codec version specific one, so the result is not in register address order because the version specific ranges overlap the base range. Regmap detects this, warns that the driver needs fixing, and sorts its own copy at runtime. Sort the concatenated array before handing it to regmap so the warning goes away and regmap does not sort a second time. The base and version specific split is kept deliberately for readability, so a static reorder is not appropriate here. Cache type for all four macro codecs: - Switch the register cache from REGCACHE_FLAT to REGCACHE_MAPLE in lpass-rx-macro, lpass-wsa-macro, lpass-tx-macro and lpass-va-macro. A flat cache hides missing default reads by returning the zero initialised cache slot instead of performing a bus read, and the caller cannot tell that value apart from a real hardware value, so any readable non-volatile register without a default silently returns wrong data. With a maple cache a miss returns -ENOENT and the regmap core falls back to a real bus read, so the caller always observes the true hardware value. Write cache behaviour is unchanged. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Add a thin LPASS clock controller driver for Glymur that exposes the reset lines required by the LPASS audio macro codecs and the SoundWire masters. The driver provides no clocks of its own and acts purely as a reset provider over two register regions. The driver registers two device tree compatibles, each with its own regmap and reset map: - qcom,glymur-lpassaudiocc covers the LPASS audio CSR region and exposes the receive path reset line together with the four WSA SoundWire reset lines. - qcom,glymur-lpasscc covers the LPASS TCSR region and exposes the transmit path SoundWire reset line. Probe resolves the per compatible controller description from the match data and hands it to the common Qualcomm clock controller probe helper, which builds the regmap and registers the reset controller. Reset identifiers come from the Glymur LPASS clock controller device tree binding header. A new SC_LPASSCC_GLYMUR Kconfig symbol builds the driver as a module by default on Qualcomm platforms, matching the other LPASS clock controller entries. These reset lines are required for the LPASS audio macros and the SoundWire compute mode controller to come out of reset on Glymur. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Enable SDCA and WCD9378 SDCA codec as module. Signed-off-by: Gopi Chandra Sekhar Reddy Kanala <gkanala@qti.qualcomm.com>
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🔨 Build Failure Analysis — PR #1877PR: #1877
VerdictThis is not a compilation failure. The build failed during the automerge (integration) step due to a merge conflict in 📎 Detailed analysis: Full report |
🔨 Build Failure Analysis — PR #1877PR: #1877
VerdictThis is NOT a compilation error. The build failed during the git automerge phase before any compilation occurred. The merge conflict is a pre-existing integration issue between the PR and the topic branch, not a defect in the PR's code itself. 📎 Detailed analysis: Full report |
PR #1877 — validate-patchPR: #1877
Final Summary
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PR #1877 — checker-log-analyzerPR: #1877
Detailed report: Full report
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🔨 Build Failure Analysis — PR #1877PR: #1877
VerdictThis is a merge conflict, not a compilation error. The PR introduces changes to 📎 Detailed analysis: Full report |
🔨 Build Failure Analysis — PR #1877PR: #1877
VerdictThis is a merge conflict, not a compilation error. The PR introduces changes to 📎 Detailed analysis: Full report |
PR #1877 — validate-patchPR: #1877
Final Summary
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PR #1877 — checker-log-analyzerPR: #1877
Detailed report: Full report
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4 participants
This series adds the infrastructure required to enable headset audio support on the Glymur platform.
It includes:
SDCA framework fixes and enhancements required for codec integration.
SoundWire updates for SDCA, multi-port, and multi-lane topologies.
LPASS macro codec support for Glymur (codec v2.9) and register cache fixes.
Device-tree binding updates for Glymur LPASS clock controller and SoundWire.
Glymur LPASS clock controller driver providing reset control for audio macros and SoundWire.
Defconfig updates enabling SDCA and WCD9378-SDCA codec support.
Together, these changes provide the software dependencies needed for Glymur audio subsystem bring-up and headset enablement.
CRs-Fixed: 4685816
Jira ticket: https://jira-dc.qualcomm.com/jira/browse/QLIJIRA-208