Enable DCC and memory dump for Nord - #1883
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Jie Gan (jiegan0107) merged 3 commits intoSep 24, 2026
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…ation Remove the CACHE_CLUSTER0-2 dump entries from Hamoa's and Glymur's dump tables; the per-cluster cache dump is redundant with the existing per-CPU CACHE_CPU0-11 entries and pushed the table size well past the reserved CMA pool. Grow the memdump CMA reservation from 0x3000000 to 0x5000000 so it covers the largest dump table (Hamoa/Glymur, now ~56MB with per-CPU SPR/cache entries for CPU0-CPU11) with headroom. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the memory dump table for the Nord platform (SoC IDs 648, 690, 691, 692, 798, 803), including new CPUSS cluster/per-CPU and GPU scandump entries in the dump_ids enum. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Add the DCC register capture list for the Nord platform (SoC IDs 648, 690, 691, 692, 798, 803) in a dedicated header qcom-dcc-nord-config.h and enable DCC support for it. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
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Add the DCC register capture list for the Nord platform (SoC IDs 648, 690, 691, 692, 798, 803) in a dedicated header qcom-dcc-nord-config.h and enable DCC support for it.