arm64: dts: qcom: lemans-draco-evk: Enable Native DP support - #1895
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Add the compatible string for the Qualcomm LeMans Draco EVK board (SA8775P/QCS9100 SoC). The compatible chain is: qcom,lemans-draco-evk qcom,lemans-draco-evk-som qcom,qcs9100 qcom,sa8775p Signed-off-by: Gopikishan Thawre <gthawre@qti.qualcomm.com>
Add build entry for the LeMans Draco EVK board DTB. Signed-off-by: Gopikishan Thawre <gthawre@qti.qualcomm.com>
Add device tree for the LeMans Draco EVK System-on-Module (SOM) based on the SA8775P/QCS9100 SoC. The SOM includes: - Complete RPMH regulator configuration for three pmm8654au PMICs: pmic-id a: smps4/5/9 and ldo4/5/6/7/8/9 pmic-id c: ldo1/2/3/4/5/6/7/8/9 pmic-id e: smps4/7/9 and ldo6/8 - Firmware paths for QUP firmware and remote processors (ADSP, CDSP0) - Debug UART (uart0) - XO board clock at 38.4 MHz, sleep clock at 32.768 kHz Signed-off-by: Gopikishan Thawre <gthawre@qti.qualcomm.com>
Add top-level board device tree and extend the SOM DTSI with peripherals for the Qualcomm LeMans Draco EVK carrier board: - Five I2C GPIO expanders on i2c2: four TCA6416-compatible at 0x20-0x23 (U236, U238, U422, U417) for camera/display MUX and power enables, one PCA9534-compatible (U445) at 0x38 for camera MCLK enables - EEPROM (U?,giantec,gt24c256c) at 0x50 with MAC address nvmem layout - uart10 as the geni-debug-uart (console) - ufs_mem_hc and ufs_mem_phy with regulator assignments - USB nodes: usb_0, usb_0_hsphy, usb_0_qmpphy, usb_2 and usb_2_hsphy - pmm8654au_2 GPIO states for USB interrupt and ID lines - Remoteproc SMMU stream IDs for ADSP, CDSP0/1, GPDSP0/1 - Correct mmc1 alias (was mmc0); serial0 -> uart10, serial2 -> uart0 - Remove pcie0, pcie1 and ethernet0 -- not present on this board Signed-off-by: Gopikishan Thawre <gthawre@qti.qualcomm.com>
Enable PCIe0 and PCIe1 on the Lemans based Draco EVK platform. PCIe0 connects to the NTN3 switch while PCIe1 can be routed either to an x4 slot or M.2 M-key slot based on dip switches configuration. Upstream-Status: Pending Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
…_config_sid_1_9_0()
qcom_pcie_config_sid_1_9_0() reads the "iommu-map" property as an array
of fixed four-word {rid-base, phandle, sid, rid-len} entries to program
the BDF to SID translation table. But that layout only holds for an
IOMMU with '#iommu-cells = <1>'. The PCIe SMMUs on these SoCs use
'#iommu-cells = <2>' (SID and mask), so per the pci-iommu binding each
entry is really five cells long.
This used to work only because the DTs were themselves broken. They
described iommu-map with four-cell entries that omitted the SID mask,
which of_map_id() tolerated via its of_check_bad_map() fallback, and the
four-word parsing coincidentally matched that malformed shape.
Since commit ccb2fd7 ("of: Respect #{iommu,msi}-cells in maps") the
OF core parses such maps correctly, so the device trees were converted
to proper five-cell entries, e.g. commit c41749e ("arm64: dts:
qcom: sm8250: Fix the PCIe iommu-map entries"). With five-cell entries
the fixed four-word stride slips by one cell for each entry after the
first, so qcom_pcie_config_sid_1_9_0() reads the endpoint mapping's RID
from the preceding entry's length cell and its SID from the phandle cell.
As the RID is the hash key, the endpoint's real RID is never programmed
into the BDF to SID table. Its DMA then hashes to an unprogrammed slot,
gets tagged with SID 0 and the SMMU faults like below on QCS8300:
arm-smmu 15200000.iommu: Unhandled context fault: fsr=0x402, iova=0xffa00000, cbfrsynra=0x0, cb=1
To fix this, walk the map with a stride of 3 + '#iommu-cells' of the
referenced IOMMU and take the SID from the first specifier cell, which is
all the BDF to SID table needs. Validate the layout instead of trusting
the array size. Also, preserve the legacy behavior of the old DTs by
detecting the same pattern that of_check_bad_map() recognizes and
falling back to a stride of four.
Fixes: 4c93988 ("PCI: qcom: Add support for configuring BDF to SID mapping for SM8250")
Reported-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260907143349.317495-1-mani@kernel.org
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Upstream-Status: Pending
Enable the M.2 E-key connectivity slot on Lemans Draco EVK by describing its always-on 3.3 V supply and PCIe and UART graph connections. Describe W_DISABLE2# so pwrseq-pcie-m2 can control Bluetooth power through UART17. Upstream-Status: Pending Signed-off-by: Wei Deng <wei.deng@oss.qualcomm.com>
…e support Enable the MDSS display subsystem on the Qualcomm Lemans Draco EVK board and add the Lontium LT9611UXD DSI-to-HDMI bridge node. Signed-off-by: Mohit Dsor <mohit.dsor@oss.qualcomm.com>
Enabled Native DP0, DP1, DP2, DP3 support for Lemans Draco EVK. Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com>
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Enabled DP0, DP1, DP2, DP3 ports.