Ethernet changes for Nord Ride SX - #1896
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Mohd Ayaan Anwar (ayaan-anwar) wants to merge 18 commits into
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Mohd Ayaan Anwar (ayaan-anwar) wants to merge 18 commits into
Mohd Ayaan Anwar (ayaan-anwar) wants to merge 18 commits into
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Add the EMAC0 and EMAC1 CNOC APB clock IDs to the SE_GCC clock controller bindings for the Qualcomm Nord SoC. Link: https://lore.kernel.org/lkml/20260824-nords_emac_apb_clk-v1-1-290767386bf5@oss.qualcomm.com/ Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Add the EMAC0 and EMAC1 CNOC APB clocks to the SE_GCC clock controller on the Qualcomm Nord SoC. These branch clocks gate the config NoC APB access to the two EMAC controllers and are required for register access to the Ethernet MACs. Link: https://lore.kernel.org/lkml/20260824-nords_emac_apb_clk-v1-2-290767386bf5@oss.qualcomm.com/ Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…mpatible Add the qcom,nord-dwmac-sgmii-phy compatible to the Qualcomm DWMAC SGMII PHY binding. Link: https://lore.kernel.org/linux-arm-msm/20260923-nord_ethernet_serdes-v1-1-f8ac1c487882@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Prepare the SGMII Ethernet PHY driver for PHY modes that require a different SerDes programming sequence. Move the SGMII readiness checks into a helper so additional modes can provide their own status checks, and select the initial interface mode through per-compatible match data rather than hardcoding SGMII during probe. This does not change existing SA8775P behavior. Link: https://lore.kernel.org/linux-arm-msm/20260923-nord_ethernet_serdes-v1-2-f8ac1c487882@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Nord uses a QMP v7 SerDes block which is an updated version of the SGMII SerDes PHY IP. The SGMII SerDes PHY supports multiple operating modes by programming different SerDes line rates. The driver currently handles SGMII and 2500BASE-X configurations only. Add support for configuring the SerDes to operate at 10.3125 Gbaud, enabling both USXGMII and 10GBASE-R PHY interface modes. Finally, add a driver compatible for Nord. Select USXGMII as the initial interface mode for Nord. phy_power_on() can run before the consumer calls set_mode(), so this ensures that the first calibration selects the 10.3125 Gbaud programming sequence. Link: https://lore.kernel.org/linux-arm-msm/20260923-nord_ethernet_serdes-v1-3-f8ac1c487882@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Document the Qualcomm Nord integrated DesignWare XPCS compatible. The XPCS resides in an Ethernet power domain and requires its CSR clock for register access, so require the clock and power-domain resources for this compatible. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-1-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Add the Clause 37 USXGMII configuration and state handling required by XPCS variants which use Clause 37 framing for USXGMII. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-2-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Some XPCS integrations do not expose the standard direct or indirect register layout. Allow the platform driver to use optional register read and write callbacks for both Clause 22 and Clause 45 accesses, while retaining the existing access paths when no callbacks are supplied. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-3-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord exposes the DesignWare XPCS register blocks through separate direct-MMIO windows instead of the standard contiguous MMD/register layout. Add accessors that translate MMD accesses to the Nord windows: MMD 3 (PCS), standard registers: SR_XS at 0x0000 MMD 3 (PCS), vendor registers: VR_XS at 0x2000 MMD 1 (PMA/PMD): SR_PMA at 0x3000 MMD 31 (VEND2), standard regs: SR_MII at 0x4000 MMD 31 (VEND2), vendor registers: VR_MII at 0x5000 Each register uses a 32-bit MMIO stride. The vendor bit is removed from the register index before calculating a vendor-window offset. Select these accessors using the Nord synthetic XPCS ID, allow its smaller direct-MMIO resource, and add the Nord USXGMII Clause 37 compatibility. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-4-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
xpcs_plat_init_clk() acquires the optional CSR clock but does not prepare or enable it. Marking the device runtime-active at that point makes the PM core assume that the hardware is already powered. On Nord, once the XPCS CSR clock was described, the first pm_runtime_resume_and_get() accessed XPCS registers without invoking runtime_resume() to enable the clock. The matching runtime put then invoked runtime_suspend() and attempted to disable a clock which was never enabled, producing an already-disabled clock warning. Initialize the runtime-PM state as suspended instead. The first register access now runs the resume callback and enables the CSR clock, while the subsequent suspend callback performs the matching disable. Check and propagate the state-transition error as part of probe. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-5-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
The DW25GMAC introduced a new DMA architecture called Hyper-DMA (HDMA) for virtualization scalability. This is realized by decoupling physical DMA channels(PDMA) from potentially large number of virtual DMA channels(VDMA). The VDMAs provide software abstraction to driver that map to PDMAs for frame transmission and reception. Since 25GMAC is a derivative of XGMAC, majority of IP is common to both. To add support for the HDMA in 25GMAC, a new instance of dma_ops, dw25gmac400_dma_ops is introduced. To support the current needs, a simple one-to-one mapping of dw25gmac's logical VDMA (channel) to TC to PDMAs is used. Most of the other dma operation functions in existing dwxgamc2_dma.c file are reused whereever applicable. Added setup function for DW25GMAC's stmmac_hwif_entry in stmmac core. Link: https://lore.kernel.org/netdev/20260402213629.1996133-2-jitendra.vegiraju@broadcom.com/ Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Integrate dw25gmac support into stmmac hardware interface handling. Added a new entry to the stmmac_hw table in hwif.c. Link: https://lore.kernel.org/netdev/20260402213629.1996133-3-jitendra.vegiraju@broadcom.com/ Signed-off-by: Jitendra Vegiraju <jitendra.vegiraju@broadcom.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord integrates two ETHQOS controllers based on the Synopsys DesignWare XGMAC IP. Each controller has five clocks, one power domain, and ten SMMU stream mappings. Due to a hardware quirk, PCS link-up depends on the EEE clock being enabled. Add the Nord compatible to the common DWMAC schema exceptions used by Qualcomm ETHQOS platforms. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-6-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Some XGMAC integrations place their MTL queues and DMA channels at different offsets from the standard register layout. Allow platform data to override these addresses while retaining the standard layout by default. This follows the approach used by commit 33719b5 ("net: stmmac: dwmac4: Allow platforms to specify some DMA/MTL offsets"). Qualcomm XGMAC hardware similarly uses differently aligned queue and channel registers. Also allow platforms to override the timestamp register base. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-7-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Select the XPCS instance initialized by stmmac when firmware provides a pcs-handle. Reject interfaces that are not supported by the selected PCS. Link: https://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-8-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord provides two ETHQOS controllers based on the Synopsys DesignWare XGMAC IP. Add their register layout, wrapper configuration for USXGMII, EEE clock handling required for PCS link-up, and platform-specific SGMII loopback control. Link: ttps://lore.kernel.org/netdev/20260923-qcom_xpcs_nord_emac-v1-9-4b1c682af70f@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Qualcomm Nord needs its DW25GMAC HDMA channels to wait for CSR initialization, configure mappings for channels not exposed to Linux, and use independent VDMA and PDMA traffic-class maps. Keep these integration-specific HDMA fixes downstream while DW25GMAC support is under review. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
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Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and SerDes blocks, clocks, resets, power domains, SMMU streams and DMA queues. Enable both ports on Nord Ride SX in fixed-link USXGMII 10-Gbps mode for connection to the onboard firmware driven Ethernet switch. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
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This PR integrates the Nord Ethernet enablement work into nord-next.
The majority of the changes have already been posted upstream as part of the SerDes and XPCS/ETHQOS first-post series. The remaining delta is intentionally limited to:
This follows the agreed upstreaming strategy of landing Qualcomm-owned workstreams incrementally rather than blocking on all external dependencies. The branch has been validated on Nord Ride SX. For Nord RRD, some more changes identified by Zhangfei are required and will be added in a follow-up PR.
CRs-Fixed: 4688350