FROMLIST: misc: fastrpc: Add cache maintenance for non-coherent platf… - #1897
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…orms Some platforms using fastrpc do not support DMA coherency on HLOS. On such systems, explicit cache maintenance is required to ensure data consistency for RPC argument buffers. Add cache maintenance for argument buffers when operating on non-coherent platforms: - Flush input buffers before invoking RPC to ensure CPU writes are visible to the DSP - Invalidate output buffers after RPC completion to ensure DSP writes are visible to the CPU Introduce helper functions fastrpc_flush_args() and fastrpc_inv_args() to perform the required dma-buf cache operations. These are invoked only when the device is not marked as DMA coherent. The coherency capability is determined using the "dma-coherent" device tree property and stored per session context. This ensures correct data synchronization on platforms lacking DMA coherency, while avoiding unnecessary overhead on coherent systems. Link: https://lore.kernel.org/all/20260916185850.3686010-1-abhinav.parihar@oss.qualcomm.com/ Signed-off-by: Abhinav Parihar <abhinav.parihar@oss.qualcomm.com>
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Dev Completion validation failed CR: 4650183 The change task for this CR could not be moved to Dev Complete because of the error above. Please resolve the issue in Orbit and re-run the failed Orbit check. |
qcomlnxci
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Chenna Kesava Raju (Chennak-quic) and
Ekansh Gupta (ekanshibu)
and removed request for
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September 24, 2026 06:44
Ekansh Gupta (ekanshibu)
approved these changes
Sep 24, 2026
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Some platforms using fastrpc do not support DMA coherency on HLOS. On such systems, explicit cache maintenance is required to ensure data consistency for RPC argument buffers.
Add cache maintenance for argument buffers when operating on non-coherent platforms:
Introduce helper functions fastrpc_flush_args() and fastrpc_inv_args() to perform the required dma-buf cache operations. These are invoked only when the device is not marked as DMA coherent.
The coherency capability is determined using the "dma-coherent" device tree property and stored per session context.
This ensures correct data synchronization on platforms lacking DMA coherency, while avoiding unnecessary overhead on coherent systems.
Link: https://lore.kernel.org/all/20260916185850.3686010-1-abhinav.parihar@oss.qualcomm.com/
CRs-Fixed: 4650183