Ethernet changes for Nord Ride SX - #1901
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Mohd Ayaan Anwar (ayaan-anwar) wants to merge 6 commits into
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Mohd Ayaan Anwar (ayaan-anwar) wants to merge 6 commits into
Mohd Ayaan Anwar (ayaan-anwar) wants to merge 6 commits into
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Mohd Ayaan Anwar (ayaan-anwar)
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September 24, 2026 07:41
Add the EMAC0 and EMAC1 CNOC APB clock IDs to the SE_GCC clock controller bindings for the Qualcomm Nord SoC. Link: https://lore.kernel.org/lkml/20260824-nords_emac_apb_clk-v1-1-290767386bf5@oss.qualcomm.com/ Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Add the EMAC0 and EMAC1 CNOC APB clocks to the SE_GCC clock controller on the Qualcomm Nord SoC. These branch clocks gate the config NoC APB access to the two EMAC controllers and are required for register access to the Ethernet MACs. Link: https://lore.kernel.org/lkml/20260824-nords_emac_apb_clk-v1-2-290767386bf5@oss.qualcomm.com/ Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…mpatible Add the qcom,nord-dwmac-sgmii-phy compatible to the Qualcomm DWMAC SGMII PHY binding. Link: https://lore.kernel.org/linux-arm-msm/20260923-nord_ethernet_serdes-v1-1-f8ac1c487882@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Prepare the SGMII Ethernet PHY driver for PHY modes that require a different SerDes programming sequence. Move the SGMII readiness checks into a helper so additional modes can provide their own status checks, and select the initial interface mode through per-compatible match data rather than hardcoding SGMII during probe. This does not change existing SA8775P behavior. Link: https://lore.kernel.org/linux-arm-msm/20260923-nord_ethernet_serdes-v1-2-f8ac1c487882@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Nord uses a QMP v7 SerDes block which is an updated version of the SGMII SerDes PHY IP. The SGMII SerDes PHY supports multiple operating modes by programming different SerDes line rates. The driver currently handles SGMII and 2500BASE-X configurations only. Add support for configuring the SerDes to operate at 10.3125 Gbaud, enabling both USXGMII and 10GBASE-R PHY interface modes. Finally, add a driver compatible for Nord. Select USXGMII as the initial interface mode for Nord. phy_power_on() can run before the consumer calls set_mode(), so this ensures that the first calibration selects the 10.3125 Gbaud programming sequence. Link: https://lore.kernel.org/linux-arm-msm/20260923-nord_ethernet_serdes-v1-3-f8ac1c487882@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
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Describe both Nord 10-Gbps Ethernet controllers, including their XPCS and SerDes blocks, clocks, resets, power domains, SMMU streams and DMA queues. Enable both ports on Nord Ride SX in fixed-link USXGMII 10-Gbps mode for connection to the onboard firmware driven Ethernet switch. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
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This PR integrates the Nord Ethernet prerequisite work into nord-next. It includes:
The remaining ethernet driver changes will come via the tech/net/eth topic branch.
For Nord RRD, some more changes identified by Zhangfei are required and will be added in a follow-up PR.
CRs-Fixed: 4688350