Prepare qcom-next based on tag 'Linux 7.3-rc4' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git - #1183
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Add initial device tree for the Qualcomm SA8797P Ride reference board, which is built on Nord GearVM variant. - Configure UART15 as the primary console and UART4 as the secondary serial port - Enable UFS storage support - Define thermal zones for PMIC dies, UFS, and two SDRAM sensors, all sourced from SCMI sensor protocol on channel 23 Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Tested-by: Yadu M G <yadu.mg@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260914031412.140856-6-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add initial device tree for the Qualcomm Dragonwing IQ10 RRD (Robotics Reference Design) board, which is built on Nord Embedded variant. Enable the debug UART, UFS storage, PMICs, I2C and SPI. Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260914031412.140856-7-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the compatible string for the GPI DMA engine found on the Nord family of SoCs. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260916-nord-gpi-dt-bindings-v1-1-857bf9e84999@oss.qualcomm.com
Add GPI DMA controller nodes for all three QUPv3 engines. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-gpi-dts-v2-1-4f297c983b94@oss.qualcomm.com
…ines Add DMA phandles to I2C and SPI QUPv3 serial engine nodes. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-gpi-dts-v2-2-4f297c983b94@oss.qualcomm.com
The Nord clock driver entries in Kconfig were out of alphabetical order. Reorder these symbols so Kconfig follows the same order as Makefile, making it easier to locate and add entries consistently. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260831134717.510383-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…r Nord The NW_GCC video axi reset clocks are required by the video SW driver to assert and deassert the clock resets during their power down sequence. Hence add these clock resets. Fixes: 06498d5 ("dt-bindings: clock: qcom: Add Nord Global Clock Controller") Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-1-674d7718e41f@oss.qualcomm.com
The global clock controller video axi reset clocks are required by the video SW driver to assert and deassert the clock resets during their power down sequence. Hence add these clock resets. Fixes: a4f780c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-2-674d7718e41f@oss.qualcomm.com
…d SoC Add compatible string for Nord video clock controller and the bindings for Nord Qualcomm SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-3-674d7718e41f@oss.qualcomm.com
…roller for Nord Update the compatible and the bindings for CAMCC support on Nord SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-4-674d7718e41f@oss.qualcomm.com
…rt for Nord Nord shares the video clock controller topology with Glymur, differing only in the PLL0 hardware (Lucid-OLE vs Taycan-EKO-T) and the MVS0 frequency table. Extend the existing Glymur video clock controller driver to also probe on the qcom,nord-videocc compatible, switching to the Nord PLL configuration, VCO table, and MVS0 frequency table at probe time. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-5-674d7718e41f@oss.qualcomm.com
…or Nord Add support for the Camera Clock Controller (CAMCC) on the Nord platform for camera SW drivers to request for these clocks. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260801-nord_videocc_camcc-v2-6-674d7718e41f@oss.qualcomm.com
Add the GPU, camera, video, and display clock controller nodes for the Qualcomm Nord SoC, along with their required dt-bindings includes. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260920081049.2183845-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add specific compatible string to document the GPU SMMU present on Nord SoC, and constrain it to the single HLOS vote clock. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260902013858.130887-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the Adreno GPU SMMMUs (MMU-500) for both GPU instances. Wire up the gpucc clock and power domain on both adreno SMMU nodes in nord-embedded.dtsi for embedded Nord variants where gpucc is available. Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260922111354.533902-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Map qcom,nord to glymur_data in qcom_ubwc_configs[], since Nord shares Glymur's UBWC capabilities. Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260903014309.314962-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…ompatible Document the qcom,nord-cpu-bwmon fallback compatible used by the CPU bandwidth monitors on Nord. Signed-off-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Georgi Djakov <djakov@kernel.org> Link: https://lore.kernel.org/r/20260831090134.585588-1-zhangfei.gao@oss.qualcomm.com
Add BWMON nodes and associated OPP tables to enable dynamic DDR/LLCC frequency scaling. The compatible is added in nord-embedded.dtsi rather than nord.dtsi, because Embedded variant specific 'interconnects' is required by the compatible. Co-developed-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> Signed-off-by: Pushpendra Singh <pussin@qti.qualcomm.com> Link: https://lore.kernel.org/r/20260922080416.484280-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Nord has four DDR slices with four MACH9 LLCC banks each, so it exposes sixteen bank regions plus the shared broadcast OR/AND pair. Add its compatible with a matching reg/reg-names group and raise the top level maxItems to eighteen. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Reviewed-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260910-nord_llcc-v1-1-30fd1cca65fe@oss.qualcomm.com
Add the sub-cache table for Nord, derived from the Nord AU (Safe IVI) SCT table and limited to the POR use cases that have a unique SCID and a usecase ID in llcc-qcom.h. Nord has the CFG0/CFG1 pairs and the full ALGO_ALLOC0..3 set, so it uses the v6 register offsets. num_banks is set explicitly because LLCC_LB_CNT in LLCC_COMMON_STATUS0 is four bits wide and cannot report sixteen banks; a wrong count makes the driver map a bank aperture in place of the broadcast region and abort on the first broadcast read. no_edac is set because the bootloader leaves the LLCC EDAC registers locked, as on Glymur. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Tested-by: Zhangfei Gao <zhangfei.gao@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260910-nord_llcc-v1-2-30fd1cca65fe@oss.qualcomm.com
Add the system cache controller. All sixteen banks are listed, four per DDR slice at 0x100000 strides from slice + 0x800000, followed by the global broadcast OR/AND regions, which the driver expects at the reg indices right after the last bank. No ECC interrupt is described, as the Nord interrupt map does not expose one for the LLCC. The driver treats it as optional. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260922091735.491481-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the top-level pmu node so perf events can be collected on Nord. Signed-off-by: Anurag Pateriya <apateriy@qti.qualcomm.com> Link: https://lore.kernel.org/r/20260922093446.493606-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…tach qcom_pas_attach() unmasks the handover IRQ and marks handover_issued even though this driver instance never runs qcom_q6v5_prepare() for the boot it is attaching to. This was believed necessary to flush a stale interrupt latched at the interrupt controller while masked, but the handover IRQ is a Qualcomm SMP2P soft IRQ, not a real edge-latched hardware interrupt. The Linux SMP2P driver updates its cached value unconditionally on every notification and only delivers the nested IRQ for bits currently enabled in its own software bitmap, so a transition that happens while masked is simply dropped, never replayed on a later unmask. Since there is nothing to flush, and this driver instance never takes the proxy power-domain/clock/regulator votes that the handover callback would tear down, there is no need to unmask the IRQ in attach() at all. Drop the enable_irq()/disable_irq() pair; setting handover_issued = true is sufficient to keep the flag consistent for the eventual qcom_q6v5_unprepare()/qcom_q6v5_prepare() cycle. It fixes the following unbalanced runtime PM usage and IRQ enable warnings seen on Nord ADSP (probed as attached), after commit bb7c5d6 ("remoteproc: qcom: q6v5: Make handover IRQ one-shot") comes in place. root@iq10-rrd:~# cat /sys/class/remoteproc/remoteproc0/state attached root@iq10-rrd:~# echo stop > /sys/class/remoteproc/remoteproc0/state [ 40.004874] genpd genpd:0:4c00000.remoteproc: Runtime PM usage count underflow! [ 40.012409] genpd genpd:1:4c00000.remoteproc: Runtime PM usage count underflow! [ 40.050074] remoteproc remoteproc0: stopped remote processor adsp root@iq10-rrd:~# echo start > /sys/class/remoteproc/remoteproc0/state [ 44.350298] remoteproc remoteproc0: powering up adsp [ 44.375769] remoteproc remoteproc0: Booting fw image qcom/nord/adsp.mbn, size 8241816 [ 44.389850] PDM: no support for the platform, userspace daemon might be required. [ 44.397864] ------------[ cut here ]------------ [ 44.402633] Unbalanced enable for IRQ 363 [ 44.406779] WARNING: kernel/irq/manage.c:775 at __enable_irq+0x4c/0x7c, CPU#9: sh/791 ... Suggested-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20260801011731.1084591-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Nord routes the NSP (compute DSP) memory rail through a dedicated NMXC resource instead of the shared MX rail. Add the index so device trees can reference it. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260826135454.658615-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the nmxc.lvl RPMh resource and register it in the Nord power domain table. Nord supplies the NSP memory rail from this dedicated resource rather than from the shared MX rail, so consumers need it exposed as its own power domain. Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260826135454.658615-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add compatible for Qualcomm PMAU0102 PMIC that is used on Nord platform. Signed-off-by: Dhruvin Rajpura <drajpura@qti.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260830034719.140213-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…O support Add compatible string for the PMAU0102 PMIC GPIO block, which has 12 GPIOs, used on Nord platform. Signed-off-by: Dhruvin Rajpura <drajpura@qti.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260830042939.144376-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add support for the PMAU0102 PMIC GPIO block, which has 12 GPIOs, used on Nord platform. Signed-off-by: Dhruvin Rajpura <drajpura@qti.qualcomm.com> Link: https://lore.kernel.org/r/20260830042939.144376-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Document MBG temperature monitor on PMAU0102 which is programming-model compatible with the one on PM8775. Signed-off-by: Dhruvin Rajpura <drajpura@qti.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260830101025.191697-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Document Qualcomm PMM8654AU PMIC RTC which is compatible with PMK8350 RTC. Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260904074541.590485-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
# Conflicts: # drivers/bluetooth/hci_qca.c
# Conflicts: # MAINTAINERS
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
# Conflicts: # arch/arm64/boot/dts/qcom/monaco-evk.dts # arch/arm64/boot/dts/qcom/monaco.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/agatti.dtsi
# Conflicts: # drivers/dma/qcom/bam_dma.c # sound/soc/qcom/sc8280xp.c
# Conflicts: # arch/arm64/configs/defconfig
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
# Conflicts: # arch/arm64/boot/dts/qcom/qcs8300-ride.dts
# Conflicts: # drivers/firmware/qcom/Kconfig
# Conflicts: # arch/arm64/configs/defconfig
# Conflicts: # arch/arm64/configs/defconfig # drivers/hwtracing/coresight/coresight-tnoc.c # drivers/interconnect/qcom/Kconfig
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
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Name SHA Commits
tech/bsp/clk b662153 14
tech/bsp/devfreq 0837ca4 7
tech/bsp/interconnect 81fc6e2 1
tech/bsp/sched 9c2e4b8 3
tech/security/firmware-smc 16b0235 9
tech/bsp/soc-infra c79b7bc 28
tech/bsp/pinctrl 79149ef 1
tech/bsp/remoteproc 8c716bc 1
tech/bus/peripherals c191e3d 10
tech/bus/pci/all 0f23f88 41
tech/bus/usb/dwc 6f24600 8
tech/bus/usb/phy b94824d 38
tech/debug/hwtracing fae0f79 27
tech/pmic/misc e7bb366 12
tech/mem/iommu d196108 10
tech/mm/audio/all 5ba9def 10
tech/mm/camss cee6189 53
tech/mm/drm 3537f0b 67
tech/mm/fastrpc fab5742 4
tech/mm/video bbe1a02 57
tech/mm/gpu e065d5a 1
tech/net/ath 722be84 7
tech/net/bluetooth e352848 8
tech/pm/pmdomain 16a7451 3
tech/pm/power 179ed43 13
tech/pm/thermal a58f3b3 8
tech/security/crypto 4c71afd 13
tech/security/ice dc34f45 14
tech/storage/all cb6192d 7
tech/all/dt/qcs6490 fdf8383 21
tech/all/dt/qcs9100 3e3223b 22
tech/all/dt/qcs8300 6a513e3 28
tech/all/dt/qcs615 c3eea9f 13
tech/all/dt/agatti 2ca1b63 2
tech/all/dt/eliza fd76dfc 18
tech/all/dt/hamoa 75cc2f2 39
tech/all/dt/glymur eaa4226 30
tech/all/dt/kaanapali b395c11 18
tech/all/dt/pakala 9cdd195 13
tech/all/shikra 0e707d3 196
tech/all/config 00643d8 86
tech/overlay/dt ae50c51 90
tech/all/workaround ebc9406 14
tech/noup/debug/all 9f1e8ae 37
tech/hwe/unoq a2d85fe 4
early/hwe/nord e1575ac 114
early/hwe/staging/nord 972aee4 119