Prepare qcom-next based on tag 'Linux 7.3-rc4' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git - #1188
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Add support for the PMAU0102 PMIC GPIO block, which has 12 GPIOs, used on Nord platform. Signed-off-by: Dhruvin Rajpura <drajpura@qti.qualcomm.com> Link: https://lore.kernel.org/r/20260830042939.144376-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Document MBG temperature monitor on PMAU0102 which is programming-model compatible with the one on PM8775. Signed-off-by: Dhruvin Rajpura <drajpura@qti.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260830101025.191697-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Document Qualcomm PMM8654AU PMIC RTC which is compatible with PMK8350 RTC. Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260904074541.590485-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add device tree nodes to support ADSP (HPASS DSP) and CDSPs remoteproc on Nord SoC. This includes: - SMEM memory reservation used by the inter-processor communication infrastructure - IPCC mailbox controller for inter-processor signalling - AOSS QMP node for load state power management - SMP2P nodes providing stop control and fault/crash interrupt signals - Remoteproc nodes with a GLINK edge and FastRPC compute contexts for userspace offload The embedded variant specific power domains, XO clock, and interconnect paths are filled in nord-embedded.dtsi. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260920084920.2201418-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable ADSP (HPASS DSP) and CDSPs remoteproc on the Nord RRD board. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260920084920.2201418-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the SPMI PMIC Arbiter node for the Nord platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260920084920.2201418-4-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…port The Nord platform is supplied by two families of PMICs on the SPMI bus: eight PMAU0102 devices on USIDs 4 to 11, and one PMM8650AU on USID 0. Add one dtsi per PMIC type, following the established one-file-per-PMIC convention, and include both of them from nord-rrd.dts. The eight PMAU0102 instances are labelled pmau0102_e through pmau0102_l after their board designators. Each one provides a GPIO controller, an ADC, and an MBG (Master Bandgap) temperature monitor that reads its die temperature through a DIE_TEMP ADC channel. The monitors use the qcom,pmau0102-mbg-tm compatible with qcom,pm8775-mbg-tm as fallback, and each is hooked up to a thermal zone. PMM8650AU is the same die as PMM8654AU, so pmm8650au_a reuses the existing pmm8654au ompatibles while the file is named after the part actually populated on the board. It provides PON with a power key, a RTC, and a GPIO controller. The resin is described but left disabled, for boards that wire it up to enable. Signed-off-by: Dhruvin Rajpura <drajpura@qti.qualcomm.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260920084920.2201418-5-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Document qcom,sa8797p-ride-embedded, the Embedded variant of the Nord SA8797P Ride board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260920084920.2201418-6-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…d board Add the initial device tree for the Nord Ride Embedded board, the non-SCMI variant of the SA8797P automotive Ride board. Enable the debug UART, UFS storage, the ADSP and CDSP remote processors, and describe the board regulators supplied by the on-board PMICs. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260920084920.2201418-7-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…ead of AMBA The Aggregator TraceNoC hardware exposes CID registers, but the Component ID value returned by the hardware is 0x00000000 instead of a valid AMBA Component ID. As a result, the device cannot be identified on the AMBA bus. Describe the Aggregator TraceNoC with a dedicated single "qcom,coresight-tnoc" compatible instead of the two-string AMBA form "qcom,coresight-tnoc", "arm,primecell". This creates the device on the platform bus so it is bound by the platform driver through its compatible string rather than as an AMBA device. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260710-fix-tracenoc-probe-issue-v6-1-41eb36fef8d9@oss.qualcomm.com
The Aggregator TNOC is bound as an AMBA device through the "qcom,coresight-tnoc", "arm,primecell" compatible. The AMBA bus reads the peripheral and component ID registers to identify and probe the device. Although the Aggregator TNOC exposes the CID registers, the Component ID value returned by the hardware is 0x00000000 instead of a valid AMBA Component ID, so the AMBA match fails and the device never comes up. Bind the Aggregator TNOC on the platform bus instead, where the device is matched by its compatible string and no component-ID probing is performed. Add "qcom,coresight-tnoc" to the platform driver's match table, and rename the platform driver and its callbacks from the "itnoc"-specific names to generic "tnoc" names, since the driver now serves both the Interconnect and Aggregator TNOC. Update the platform driver name to "coresight-tnoc" accordingly. The ATID-unsupported handling keyed off dev_is_amba(), which disabled ATID allocation for every platform-bus device. With the Aggregator TNOC now on the platform bus, that check would wrongly disable its ATID, even though the Aggregator TNOC owns the ATID that tags the whole aggregation path. The Interconnect TNOC aggregates trace within its subsystem but carries no ATID of its own, because the downstream Aggregator TNOC already owns the ATID for the path. So base the check on the "qcom,coresight-itnoc" compatible and let every other form allocate a trace ID. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Reviewed-by: Leo Yan <leo.yan@arm.com> Link: https://lore.kernel.org/r/20260710-fix-tracenoc-probe-issue-v6-2-41eb36fef8d9@oss.qualcomm.com
The CTCU device for nord shares the same configurations as SA8775p. Add a fallback to enable the CTCU for nord to utilize the compatible of the SA8775p. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260922100850.527109-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the CoreSight trace topology for the Qualcomm Nord SoC: CTCU, STM, TPDM/TPDA sources and aggregators, funnels, replicators, TMC ETR/ETF sinks, TNoC/ITNoC nodes and per-subsystem CTIs. This wires up trace sources for SOCCP, BCV/IMH/DPM, GCC, QM, DL_NOC, the CDSP NSP0-3 clusters, DLMM, EVA, MDSS0/1, LPASS and the AOSS SWAO priority TPDMs, plus the DDR0-3 channel and LLCC TPDMs, all funneled through the tn_ag aggregator into the main CoreSight funnel and out to the AOSS sink. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260922100850.527109-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…B2 PHY reset The NE_GCC block has two eUSB2 PHY block resets - PRIM and SEC - but right now only the primary is registered. Add the secondary, which is required by the usb_1 eUSB2 PHY. Note that the SoC has three eUSB2 PHYs but only these two QUSB2PHY resets: the HS-only USB20 tile has no dedicated QUSB2PHY reset and is instead reset as a whole via NE_GCC_USB20_PRIM_BCR. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260901035322.654-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the secondary USB2 PHY reset which is needed by usb_1_hsphy enabling on Nord platform. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260901035322.654-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…SB2 PHY Add a compatible for the eUSB2 PHY found on the Qualcomm Nord SoC. It is compatible with the sm8550 eUSB2 PHY. While at it: On Nord SoC there are three eUSB2 PHYs but only two QUSB2PHY block resets: the HS-only USB20 tile has no dedicated PHY reset and is instead reset as a whole through the controller's own USB20_PRIM_BCR. Make the 'resets' property optional for qcom,nord-snps-eusb2-phy only, keeping it required for all the other compatibles. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-usb-phy-v3-1-68aa02b12b96@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…he Nord QMP PHY Add a compatible for the USB3+DP combo QMP PHY found on the Qualcomm Nord SoC. The PHY sits behind a GDSC, so also allow (and require) power-domains for it. The block gets a standalone compatible rather than a fallback to an existing one, because it is not register-compatible with any PHY already described here. Its USB3 and DP initialisation sequences do match sm8550, but Nord places the sub-blocks at different offsets within the PHY: it exposes a dedicated USB3_PCS_AON region at 0x1e00, which sm8550 does not have at all. Falling back to sm8550 - or to any other entry - would make the driver program the wrong addresses. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Assisted-by: LLM Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-usb-phy-v3-2-68aa02b12b96@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Nord SoC provides two USB3+DP combo PHYs. Their initialisation sequences are identical to sm8550, but the sub-blocks are not laid out the same way: Nord adds a dedicated USB3_PCS_AON region at offset 0x1e00 and leaves everything else where sm8550 has it. None of the existing offsets tables describe that, so add a v6 table which is the v3 layout plus usb3_pcs_aon. Populating usb3_pcs_aon changes where the driver drives the I/O clamp when entering and leaving autonomous mode: it now uses the real AON region rather than falling back to PCS_MISC, which is what platforms with no AON region do. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Assisted-by: LLM Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260921-nord-usb-phy-v3-3-68aa02b12b96@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…ntroller Add a compatible for the DWC3 USB controller found on the Qualcomm Nord SoC. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260917-nord-usb-dwc3-dt-v2-1-8f88aa30c434@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
…ller The FUSB15201 is an autonomous dual-port USB Type-C and Power Delivery controller. It runs the Type-C state machine and the Power Delivery policy engine on an integrated microcontroller, and exposes only a status and command interface over I2C, so it is not a TCPC. Describe the two ports as addressed connector child nodes, so that a board which wires up only one of them can describe just that one. Assisted-by: LLM Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260916135918.1017527-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The FUSB15201 is a dual-port USB Type-C and Power Delivery controller which runs the Type-C state machine and the PD policy engine on an integrated microcontroller. The host only observes the resulting state and may ask for role swaps, so this is a plain Type-C class driver rather than a TCPC driven by the Type-C Port Manager. Register a Type-C port for each connector described in firmware, report attach and detach, orientation, power and data roles and the PD capability of the partner, and drive the USB role switch of the attached USB controller so that OTG role switching works. Data and power role swaps requested through sysfs are forwarded to the controller, which performs them asynchronously and reports the outcome as a port status interrupt. The controller exposes a per-port VBUS ADC reading, but the Type-C class has no VBUS attribute and nothing needs the value, so it is not read. PD messages, PDOs and alternate modes are not exposed by the hardware at all. The chip-wide MASTER_RESET command would drop both ports at once and has no caller, so it is left alone as well. Assisted-by: LLM Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Link: https://lore.kernel.org/r/20260916135918.1017527-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the base nodes for the three DWC3 USB controllers. These carry only the SoC-invariant properties and are disabled by default. The extension for the embedded Nord variant and relevant board files will add the platform resources and enable them. USB_2 has no SuperSpeed PHY and no 'ss_phy_irq' on this SoC, so it is capped to high-speed and told to use UTMI as its pipe clock. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911142040.100263-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add the platform resources for the three USB controllers on the embedded Nord variant: clocks, resets, power domains and interconnect paths. Add the eUSB2 PHY for each of the three controllers, plus the QMP combo PHYs for USB_0 and USB_1, and feed the two QMP USB3 pipe clocks back into negcc, which so far carried placeholder zeros in their place. The eUSB2 PHY of instance 2 gets no 'resets': the SoC provides only two QUSB2PHY block resets, belonging to instances 0 and 1. Instance 2 comes out of reset with the rest of the USB20 tile, driven by the controller. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911142040.100263-4-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Describe the RRD USB topology. Enable i2c9 and add the two NXP PTN3222 eUSB2 repeaters for USB_0 and USB_1, supplied from vreg_l3l_1p8 and a new fixed 3.3 V pre-regulator, and reset through pmau0102_i GPIOs 9 and 10. Add the onsemi FUSB15201 Type-C controller at 0x50 with its interrupt and pinctrl state on pmau0102_i gpio8. Unlike RIDE, only port A of the controller is wired on this board, to USB_0, so a single usb-c-connector is described and port B is left out. USB_0 is configured for OTG with usb-role-switch and its HS and SS endpoints are linked to the dwc3 HS endpoint and the QMP combo PHY SS output. USB_1 is a fixed host port feeding an on-board Genesys Logic GL3590 USB 3.1 hub. Add the HS and SS hub pair as children of USB_1, linked with peer-hub, with the HS half reset via TLMM GPIO 170 and the SS half additionally supplied by a fixed 1.2 V rail. Assisted-by: LLM Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911142040.100263-5-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Wire up the board specific pieces for USB ports. Enable i2c9 and add the three NXP PTN3222 eUSB2 repeaters (one per USB port) with their 1.8 V supply and reset GPIOs on the PMIC GPIO expanders. Add the onsemi FUSB15201 dual port Type-C controller at 0x50, with its interrupt and pinctrl state on pmau0102_i gpio8. Both controller ports are wired on this board, so describe two usb-c-connector children and cross-link their HS and SS endpoints to the dwc3 HS endpoint and the QMP combo PHY SS output of USB_0 and USB_1. Both controllers therefore run in OTG mode with usb-role-switch. USB_2 has no Type-C connector, so it is configured as a fixed host port. Its VBUS is supplied by a fixed regulator gated by pmau0102_h gpio3, kept always-on since nothing switches it at runtime. Assisted-by: LLM Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260911142040.100263-6-shengchao.guo@oss.qualcomm.com Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
This fixes "arm64: dts: qcom: nord: Add the USB controller nodes". Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable onsemi FUSB15201 Type-C controller driver which is needed by Qualcomm Nord Ride and RRD reference design boards. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The PCM1681 can use an external system clock supplied on the SCK input pin. Platforms that provide this clock need a way to describe the clock connection in Device Tree. Document the optional 'clocks' and 'clock-names' properties and define the clock name as "sck" to represent the external system clock source. This allows boards using an externally supplied SCK clock to accurately describe the hardware configuration. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260907-nord-asoc-driver-support-v1-2-997d3b20cf43@oss.qualcomm.com
The PCM1681 DAC requires the SCK (system clock) input to be present for proper device operation. On platforms where SCK is provided by a controllable clock source, register accesses over I2C may fail when the clock is not enabled. Add optional clock support to the PCM1681 driver by acquiring the "sck" clock, enabling it during probe, and registering a managed cleanup action to disable it during device removal or probe failure. This allows platforms to model the PCM1681 system clock through the common clock framework and ensures the device is operational before regmap initialization and register accesses occur. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260907-nord-asoc-driver-support-v1-3-997d3b20cf43@oss.qualcomm.com
Document the bindings for the Qualcomm Nord Ride board specific sound card. The bindings are the same as for other newer Qualcomm ADSP sound cards, thus keep them in existing qcom,sm8250.yaml file. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260907-nord-asoc-driver-support-v1-4-997d3b20cf43@oss.qualcomm.com
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
# Conflicts: # arch/arm64/boot/dts/qcom/monaco-evk.dts # arch/arm64/boot/dts/qcom/monaco.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/agatti.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile # drivers/remoteproc/qcom_q6v5_pas.c
# Conflicts: # drivers/dma/qcom/bam_dma.c # drivers/interconnect/qcom/Kconfig # sound/soc/qcom/sc8280xp.c
# Conflicts: # arch/arm64/configs/defconfig
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile
# Conflicts: # arch/arm64/boot/dts/qcom/qcs8300-ride.dts
# Conflicts: # drivers/firmware/qcom/Kconfig
# Conflicts: # arch/arm64/configs/defconfig
# Conflicts: # Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml # arch/arm64/configs/defconfig # drivers/hwtracing/coresight/coresight-tnoc.c # drivers/interconnect/qcom/Kconfig
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Test Matrix
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Test Matrix
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Test Matrix
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Name SHA Commits
tech/bsp/clk b662153 14
tech/bsp/devfreq 0837ca4 7
tech/bsp/interconnect 81fc6e2 1
tech/bsp/sched 9c2e4b8 3
tech/security/firmware-smc 16b0235 9
tech/bsp/soc-infra c79b7bc 28
tech/bsp/pinctrl 79149ef 1
tech/bsp/remoteproc 8c716bc 1
tech/bus/peripherals c191e3d 10
tech/bus/pci/all 0f23f88 41
tech/bus/usb/dwc 6f24600 8
tech/bus/usb/phy b94824d 38
tech/debug/hwtracing fae0f79 27
tech/pmic/misc e7bb366 12
tech/mem/iommu d196108 10
tech/mm/audio/all 5ba9def 10
tech/mm/camss 73f9fb0 54
tech/mm/drm d42e9c7 68
tech/mm/fastrpc fab5742 4
tech/mm/video bbe1a02 57
tech/mm/gpu e065d5a 1
tech/net/ath 722be84 7
tech/net/bluetooth e352848 8
tech/pm/pmdomain 16a7451 3
tech/pm/power 179ed43 13
tech/pm/thermal 2602b17 9
tech/security/crypto 4c71afd 13
tech/security/ice dc34f45 14
tech/security/optee-next 9babb9a 1
tech/storage/all cb6192d 7
tech/all/dt/qcs6490 fdf8383 21
tech/all/dt/qcs9100 3e3223b 22
tech/all/dt/qcs8300 6a513e3 28
tech/all/dt/qcs615 c3eea9f 13
tech/all/dt/agatti 2ca1b63 2
tech/all/dt/eliza fd76dfc 18
tech/all/dt/hamoa 75cc2f2 39
tech/all/dt/glymur e69025f 30
tech/all/dt/kaanapali b395c11 18
tech/all/dt/pakala 9cdd195 13
tech/all/hawi d594f58 20
tech/all/shikra 5e50e3f 198
tech/all/config 00643d8 86
tech/overlay/dt ae50c51 90
tech/all/workaround ebc9406 14
tech/noup/debug/all 9f1e8ae 37
tech/hwe/unoq a2d85fe 4
early/hwe/nord e1575ac 114
early/hwe/staging/nord 972aee4 119