[max-models]

Part 3 of 8 of the split of #772 (cuda-aware-mpi-fixes) into stacked PRs. Requires struphy-hub/feectools#104 to be merged into feectools devel-tiny first (PR 1 bumps the submodule).

• kernel_3d_mat_cuda.cu: one thread per (element, codomain basis function, domain basis function). It replaces the host fallback on the CuPy backend (missing_cuda="fallback" removed, launch size from n_threads_from).
• WeightedMassOperator.assemble reads the quadrature grids (spans, weights, basis values) as backend arrays, copied to the device once and cached.
• Simulation.allocate compiles the assembly kernel before the first assembly, in its own profiling region (setup: compile cuda kernels (assembly)), so the ~1 s compilation is not counted in the assembly.

Added while splitting: parity cases for kernel_3d_mat (random quadrature data on 3×2×2 elements with mixed degrees, with and without a ghost row). test_cuda_kernels_have_parity_cases requires one for every kernel with a CUDA version. The emulation test confirms that the CUDA kernel matches the pyccel kernel without a GPU.

Tests

Local, macOS without a GPU, in a fresh environment with feectools 1d8d47c and the pinned cunumpy, after merging devel (with #774 and #775). The PR passes test_cuda_parity, test_cuda_emulation, test_kernel_backends, test_sorting, test_accum_matrix_cupy, test_preconditioner_cupy, test_poisson and test_output on its own. The top of the stack also passes the mass-matrix, preconditioner, Derham-GPU, fused-gradient, Kronecker-block, Poisson, shear Alfvén, post-processing, polar fake-CuPy and all pic tests (1477 passed), the examples test for the two profiling cases, the sorting, Poisson and fused-gradient tests under mpirun -n 2, and the device MPI sort on the fake CuPy on 2 and 4 ranks. The Kronecker products match the stencil mass matrices to 5e-16 for M0, M1, M2, M3, Mv, M1n and M2n on a Cuboid, periodic and Dirichlet, on 1 and 2 ranks.
Not tested on a GPU here. The CUDA kernels and the device paths need a run on the cluster.

Stack (merge in order)

0. Device ghost-exchange plans, fused block exchanges, single-reduction PCG (CUDA-aware MPI) feectools#104 (feectools, into devel-tiny)

#	PR	base
1	#782 update feectools (device ghost exchange, single-reduction PCG); pcg_sr solver option	devel
2	#783 host/device conversions in post-processing; math.sqrt in Species	#782
3	#784 CUDA mass-matrix assembly kernel kernel_3d_mat (this PR)	#783
4	#785 apply separable mass matrices as Kronecker products of 1D banded matrices	#784
5	#786 Poisson/diffusion solve with fewer passes over the vectors	#785
6	#787 marker rows prepared inside the push kernels	#786
7	#788 chunked marker loading, row-based weight update, leaner MPI sorting; static field in PushVxB	#787
8	#789 profiling cases Poisson cube and Vlasov slab (CPU node vs GPU, GPU scaling)	#788

🤖 Generated with Claude Code