audio: math: add RISC-V SIMD, vector, and DSP optimizations

[lgirdwood]

Description

This series introduces architecture-accelerated SIMD, vector, and DSP math optimizations for RISC-V cores (CONFIG_RISCV).

Previously, these optimizations were developed within board-bringup branches and PRs (such as #11194 and #11200) alongside platform drivers, static topologies, and USB classes. To facilitate focused review and upstream merging, this series isolates the generic audio processing and math kernels into 8 atomic, module-by-module commits cleanly rebased onto upstream main.

All board, platform, and application-specific code has been eliminated. The optimizations target standard RISC-V DSP execution, with vendor extensions (such as ESP32-P4 PIE 128-bit vector SIMD) conditionally guarded.

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Module-by-Module Summary

1. include: common: introduce RISC-V SIMD configuration macros

   • Adds SOF_CONFIG_RISCV_SIMD(component) and SOF_USE_RISCV_SIMD(component) macros mirroring SOF_CONFIG_HIFI / SOF_USE_HIFI for compile-time optimization selection.

2. math: iir: add RISC-V SIMD cascaded DF1 and DF2T biquad filtering

   • Implements Direct Form 1 (iir_df1_riscv.c) and Transposed Direct Form 2 (iir_df2t_riscv.c) biquads.
   • Employs 64-bit MAC accumulators with branchless saturation (sat_clamp_q31) using compiler branch prediction (__builtin_expect).
   • Unrolls series biquads and optimizes FIR filtering with packed 32-bit coefficient loads. Adds CONFIG_FILTER_RISCV_SIMD.

3. include: math: add ESP32-P4 PIE 128-bit vector SIMD definitions

   • Adds src/include/sof/math/esp32p4_pie.h defining 128-bit vector instructions (PIE / Xespv2p2) using .word machine directives.
   • Guarantees 100% build compatibility with standard upstream Zephyr SDK GCC without custom toolchain patches. Adds CONFIG_ESP32P4_PIE_SIMD.

4. audio: volume: add RISC-V SIMD and contiguous vector streaming

   • Implements contiguous stereo vector streaming ($L_0, R_0, L_1, R_1$), preloading channel gains into CPU registers to eliminate strided loops.
   • Fast branchless saturation for S16, S24, and S32 formats.
   • Integrates 128-bit PIE vector SIMD acceleration (vldbc.32.ip, vmul.s16, vclamp.s16, vst.128.ip) when enabled. Adds CONFIG_VOLUME_RISCV_SIMD.

5. audio: eq_iir: add RISC-V block-accelerated processing and branchless saturation

   • Implements block processing (EQ_IIR_BLOCK_SIZE = 64) keeping filter delay states (y_n2, y_n1, x_n2, x_n1) and coefficients in registers across each block, eliminating ~98% of RAM load/store traffic.
   • Inlines biquad processing to eliminate 96 external function dispatches per millisecond. Adds CONFIG_EQ_IIR_RISCV_SIMD.

6. audio: drc: add RISC-V SIMD and fast polynomial math optimizations

   • Implements fast Horner polynomial evaluations for fixed-point transcendental math (log10_fixed, drc_lin2db_fixed, drc_log_fixed, drc_asin_fixed, drc_inv_fixed).
   • Adds fast knee_curveK, volume gain, and envelope tracking.
   • Vectorized 4-sample unrolled output compression stage. Adds CONFIG_DRC_RISCV_SIMD.

7. audio: up_down_mixer: add ANSI C and RISC-V upmix and downmix routines

   • Replaces 29 non-HiFi sof_panic(0) stubs with working ANSI C & RISC-V upmix, downmix, and shift-copy routines across all surround channel geometries (1, 2.0, 3.0, 4.0, 5.0, 5.1, 7.1) for both 16-bit and 32-bit audio.

8. audio: modules: optimize loop unrolling and guards for RISC-V dual-issue pipelines

   • 4-way loop unrolling in ASRC FIR filters (asrc_fir_filter16, asrc_fir_filter32).
   • 4-way loop unrolling and SOF_USE_RISCV_SIMD(VOLUME) guards in Level Multiplier.
   • 4x and 8x loop unrolling for integer PCM conversions (s16_to_s24, s24_to_s16, s16_to_s32, s32_to_s16, s24_to_s32, s32_to_s24).
   • Updates fallback guards for SOF_USE_RISCV_SIMD(FILTER) in EQ FIR.

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Measured Hardware Performance (Physical Silicon)

Benchmarks measured on 400 MHz physical RISC-V silicon:

Module	Optimization	Baseline (Generic C)	RISC-V Accelerated	Delta / Speedup
Volume (PIE SIMD)	128-bit vector loop	127 cycles (0.24 cyc/sample)	15 cycles (0.02 cyc/sample)	8.46x faster (0 LSB delta)
DRC	Horner polynomial & 4x unroll	44.22 MCPS	18.88 MCPS	-57.2% overhead
EQ IIR	In-register block vector	94.18 MCPS	73.27 MCPS	-22.2% overhead

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Verification

• Toolchain: Built with standard upstream Zephyr SDK GCC (no custom -march or toolchain patches required).
• Hardware: Validated on hardware audio bridges across I2S, PDM, and DMIC modes with automated bit-exact and SNR loopback tests.

[Copilot]

🟡 Changes recommended

Default builds can fail, and multiple optimized volume, EQ, and mixer paths currently produce invalid or misrouted audio.

15 open findings

• Produce high-aligned S32 output in 16-bit fallback paths · New
• Handle all supported input channel geometries · New
• Restrict ESP32-P4-specific SIMD dependency to ESP32-P4 targets · New
• Fix missing default float API and state integration · New
• Use 64-bit accumulation for parallel biquad branches · New
• Prevent Q1.31 rounding overflow before S16 conversion · New
• Prevent int32 overflow during rounded S24 conversion · New
• Derive 5.1 output order from the configured channel map · New
• Widen IPC3 gain multiplication before saturation · New
• Restrict PIE conversion to Q8.16 sub-unity gains · New
• Clamp widened result before narrowing to S24 · New
• Include math.h for fabsf declaration · New
• Prevent overflow in IPC3 gain multiplication · New
• Clamp IPC3 result before narrowing to int32 · New
• Add RISC-V defaults to the active Kconfig choice · New

What changed in this PR

Adds RISC-V-optimized audio processing kernels and ESP32-P4 PIE SIMD support.

Changes:

• Adds RISC-V IIR, EQ, DRC, volume, mixer, FIR, and conversion paths.
• Introduces RISC-V/PIE configuration and dispatch controls.
• Unrolls several generic processing loops.

File	Description
src/​platform/​Kconfig	Adds ESP32-P4 PIE option.
src/​math/​Kconfig.simd	Adds RISC-V filter selection.
src/​math/​Kconfig	Adds RISC-V filter option.
src/​math/​iir_df2t_riscv.c	Implements RISC-V DF2T IIR.
src/​math/​iir_df1_riscv.c	Implements RISC-V DF1 IIR.
src/​math/​fir_generic.c	Unrolls FIR processing.
src/​math/​CMakeLists.txt	Includes RISC-V IIR sources.
src/​include/​sof/​math/​iir_df2t.h	Selects RISC-V DF2T helpers.
src/​include/​sof/​math/​iir_df2t_riscv.h	Adds DF2T format wrappers.
src/​include/​sof/​math/​iir_df1.h	Selects RISC-V DF1 helpers.
src/​include/​sof/​math/​iir_df1_riscv.h	Adds DF1 format wrappers.
src/​include/​sof/​math/​fir_generic.h	Enables generic FIR for RISC-V.
src/​include/​sof/​math/​esp32p4_pie.h	Defines PIE instruction wrappers.
src/​include/​sof/​common.h	Adds RISC-V SIMD macros.
src/​audio/​volume/​volume_riscv.c	Adds optimized volume processing.
src/​audio/​volume/​volume_riscv_with_peakvol.c	Adds volume and peak metering.
src/​audio/​volume/​Kconfig.simd	Adds RISC-V volume selection.
src/​audio/​volume/​CMakeLists.txt	Selects RISC-V volume sources.
src/​audio/​up_down_mixer/​up_down_mixer_hifi3.c	Adds generic mixer fallbacks.
src/​audio/​pcm_converter/​pcm_converter_generic.c	Unrolls PCM conversions.
src/​audio/​level_multiplier/​level_multiplier-generic.c	Unrolls level multiplication.
src/​audio/​eq_iir/​Kconfig.simd	Adds RISC-V EQ option.
src/​audio/​eq_iir/​Kconfig	Sources EQ SIMD configuration.
src/​audio/​eq_iir/​eq_iir_riscv.c	Adds block-based RISC-V EQ.
src/​audio/​eq_iir/​CMakeLists.txt	Selects RISC-V EQ source.
src/​audio/​eq_fir/​eq_fir.h	Enables generic FIR for RISC-V.
src/​audio/​eq_fir/​eq_fir_generic.c	Enables generic EQ FIR path.
src/​audio/​drc/​Kconfig.simd	Adds RISC-V DRC option.
src/​audio/​drc/​drc_riscv.c	Adds optimized DRC processing.
src/​audio/​drc/​drc_math.h	Adds RISC-V fixed-point helpers.
src/​audio/​drc/​drc_math_riscv.c	Adds optimized DRC math.
src/​audio/​drc/​drc_generic.c	Exposes shared RISC-V DRC logic.
src/​audio/​drc/​CMakeLists.txt	Includes RISC-V DRC sources.
src/​audio/​asrc/​asrc_farrow_generic.c	Unrolls ASRC FIR loops.

🧠 Review effort: Balanced

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[lgirdwood]

PR Update & Review Comments Resolution

Thank you for the detailed review! All 15 findings have been addressed, and the series has been rebased and updated:

1. Focus on RISC-V SIMD (Dropped up_down_mixer commit):

   • Dropped audio: up_down_mixer: add ANSI C and RISC-V upmix and downmix routines from this PR series. This keeps the PR strictly focused on RISC-V SIMD optimizations; any IPC4 up/down mixer channel routing and fallback fixes will be submitted in a separate dedicated module PR.

2. Kconfig Dependencies & Defaults:

   • ESP32-P4 PIE: Removed || RISCV so CONFIG_ESP32P4_PIE_SIMD strictly depends on PLATFORM_ESP32P4 || SOC_SERIES_ESP32P4, preventing generic RISC-V targets from attempting to execute unsupported PIE vector opcodes.
   • Math Kconfig: Added default FILTER_RISCV_SIMD if RISCV to the active FILTER_SIMD_LEVEL_SELECT choice in src/math/Kconfig.

3. Volume Kernels (volume_riscv.c, volume_riscv_with_peakvol.c):

   • Widened intermediate multiplication to 64-bit (int64_t)x * vol before rounding and saturation to prevent signed overflow with IPC3 / Q8.16 gains above unity.
   • Guarded PIE vectorization to only execute when CONFIG_COMP_VOLUME_Q8_16 is active and gain is strictly < 65536 (sub-unity).
   • Widened sat_clamp_s24 parameter to int64_t to saturate widened 64-bit multiplication results before narrowing to 24-bit / 32-bit.
   • Added #include <math.h> in volume_riscv_with_peakvol.c for fabsf().

4. EQ-IIR Kernel (eq_iir_riscv.c):

   • Removed the unsupported #if CONFIG_FORMAT_FLOAT routines and header include since float state members are not part of upstream comp_data.
   • Switched parallel biquad branch accumulation buffer to int64_t accum[EQ_IIR_BLOCK_SIZE] in S16, S24, and S32 block kernels, preventing 32-bit overflow when summing parallel filter branches before final saturation.
   • Replaced manual rounding with sat_clamp_s16((int32_t)Q_SHIFT_RND(val, 31, 15)) and sat_clamp_s24((int32_t)Q_SHIFT_RND(val, 31, 23)) on widened val = (int64_t)sat_clamp_q31(accum[n]) to prevent signed 32-bit overflow on positive full scale.

All 7 atomic commits are signed off by Liam Girdwood <lgirdwood@gmail.com>.

[intel-sofci]

PR 11300: test results

Run date: 2026-10-14 21:35 UTC

Tested commit: 83265b9188b60ea86809193af9a709b864f55474

[Copilot]

🟡 Changes recommended

SIMD accuracy, unsafe FIR coefficient loads, DRC selection, and arithmetic correctness issues remain.

7 open findings

• Prevent overflow in Q21-to-Q24 compression conversion · New
• Avoid strict-aliasing violation when loading coefficients · New
• Avoid unaligned packed coefficient loads · New
• Preserve per-branch saturation in DF2T processing · New
• Select the RISC-V SIMD DRC implementation by default · New
• Preserve scalar rounding in vector gain conversion · New
• Share configuration and setup code with generic implementation · New

15 resolved since last review

• Restrict ESP32-P4-specific SIMD dependency to ESP32-P4 targets
• Handle all supported input channel geometries
• Produce high-aligned S32 output in 16-bit fallback paths
• Add RISC-V defaults to the active Kconfig choice
• Clamp IPC3 result before narrowing to int32
• Prevent overflow in IPC3 gain multiplication
• Include math.h for fabsf declaration
• Clamp widened result before narrowing to S24
• Restrict PIE conversion to Q8.16 sub-unity gains
• Widen IPC3 gain multiplication before saturation
• Derive 5.1 output order from the configured channel map
• Prevent int32 overflow during rounded S24 conversion
• Prevent Q1.31 rounding overflow before S16 conversion
• Use 64-bit accumulation for parallel biquad branches
• Fix missing default float API and state integration

🧠 Review effort: Balanced

[lgirdwood]

Addressed review comments from the latest review pass:

1. DRC max attack saturation (src/audio/drc/drc_riscv.c): Widened compression_diff_db to 64-bit and used sat_int32(Q_SHIFT_LEFT(...)) to prevent signed 32-bit shift overflow on large compression differences (>128 dB), matching generic behavior.
2. FIR strict-aliasing and alignment (src/math/fir_generic.c): Replaced packed uint32_t coefficient pointer casts with declared int16_t loads across all circular-buffer segments in fir_32x16 and fir_32x16_2x, eliminating strict-aliasing violations and preventing 2-byte unaligned accesses.
3. IIR DF2T per-branch saturation (src/math/iir_df2t_riscv.c): Preserved per-branch saturation in the parallel biquad branch loop (out = sat_clamp64((int64_t)out + in)) to conform to the generic DF2T saturation contract.
4. DRC Kconfig defaults (src/audio/drc/Kconfig.simd): Added default DRC_HIFI_MAX if XTENSA, default DRC_RISCV_SIMD if RISCV, and default DRC_HIFI_NONE to the DRC choice, and added depends on RISCV to DRC_RISCV_SIMD.
5. Volume bit-exactness (src/audio/volume/volume_riscv.c): Dropped the truncated PIE Q15 approximation path in vol_s16_to_s16; both stereo and mono now use the 4-way unrolled scalar loop with vol_mult_s16, ensuring 100% bit-exactness and proper rounding across all gain values.
6. EQ-IIR code duplication (src/audio/eq_iir/): Moved common configuration parsing, validation, setup, and delayline lifecycle functions from eq_iir_generic.c to eq_iir.c. Removed duplicate setup code from eq_iir_riscv.c so it solely provides the optimized processing routines (eq_iir_s16_default, eq_iir_s24_default, eq_iir_s32_default).

[Copilot]

🟡 Changes recommended

Modular RISC-V builds omit required implementations, privileged CSR access violates the shared-math boundary, and float peak conversion can invoke undefined behavior.

8 open findings

• Add RISC-V volume sources to the LLEXT target · New
• Move privileged CSR access out of the shared math header · New
• Move PIE CSR control out of the shared math header · New
• Add RISC-V IIR sources to the LLEXT target · New
• Clamp float peaks before converting to Q1.31 · New
• Add RISC-V DRC math accuracy tests · New
• Add RISC-V EQ-IIR reference-vector and wrap tests · New
• Add RISC-V volume processing test coverage · New

7 resolved since last review

• Preserve per-branch saturation in DF2T processing
• Avoid unaligned packed coefficient loads
• Avoid strict-aliasing violation when loading coefficients
• Prevent overflow in Q21-to-Q24 compression conversion
• Preserve scalar rounding in vector gain conversion
• Select the RISC-V SIMD DRC implementation by default
• Share configuration and setup code with generic implementation

🧠 Review effort: Balanced

[lgirdwood]

PR Update & Review Comments Resolution (Pass 3)

Addressed all review findings and CI build checks:

1. Volume LLEXT Target (src/audio/volume/llext/CMakeLists.txt):

   • Added if(CONFIG_VOLUME_RISCV_SIMD) to select ../volume_riscv.c and ../volume_riscv_with_peakvol.c for modular CONFIG_COMP_VOLUME=m builds, ensuring volume_func_map and volume_func_count are properly defined for LLEXT targets. Also updated src/audio/drc/llext/CMakeLists.txt and src/audio/eq_iir/llext/CMakeLists.txt.

2. Privileged CSR Access in Math Header (src/include/sof/math/esp32p4_pie.h):

   • Removed esp_pie_enable() and esp_pie_disable() containing csrw 0x7F2. PIE coprocessor lifecycle and state management belong in the platform HAL/kernel startup rather than the shared math header, adhering to the user-space safety boundary in src/math/README.md.

3. IIR LLEXT Target (src/math/iir_llext/CMakeLists.txt):

   • Added ../iir_df1_riscv.c to df1 and ../iir_df2t_riscv.c to df2t so modular CONFIG_MATH_IIR=m builds include RISC-V implementations.

4. Float Peak Conversion Clamp (src/audio/volume/volume_riscv_with_peakvol.c):

   • Clamped float peak values (peak = MIN(peak, 1.0f); and peak_l = MIN(peak_l, 1.0f); peak_r = MIN(peak_r, 1.0f);) before converting to the Q1.31 integer representation to prevent undefined float-to-int32 overflow when input exceeds 0 dBFS.

5. Upstream Circular Buffer API Synchronization (src/audio/eq_iir/eq_iir.c):

   • Synchronized shared eq_iir_setup() and eq_iir_pass() in eq_iir.c with the upstream circular buffer API (const struct cir_buf_source *source, struct cir_buf_sink *sink, size_t frames) and unsigned int nch, fixing conflicting type errors in host tools, ALSA plugin, and testbench builds.

6. Target SIMD Test Scope Clarification:

   • Host CMocka (test/cmocka/) executes native x86 generic reference algorithms across Xtensa defconfigs (test/test-all-defconfigs.sh). Target architecture SIMD kernels (HiFi, ARM Cortex-M DSP, RISC-V SIMD) are verified against reference vectors via Zephyr ZTest and hardware test suites.