Dynamic Instrumentation Tool Platform
a high performance library for building cache simulators
SST Architectural Simulation Components and Libraries
RISC-V simulator and IDE for learning assembly — RV32IMF, step-by-step debugger,cache , pipeline, multi-core simulator
A low-latency LRU approximation cache in C++ using CLOCK second-chance algorithm. Multi level cache too. Up to 2.5 billion lookups per second.
A C++11 simulator for a variety of CDN caching policies.
Haystack is an analytical cache model that given a program computes the number of cache misses.
cache analysis platform developed at Emory University and CMU
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
Source code for the evaluated benchmarks and proposed cache management technique, GRASP, in [Faldu et al., HPCA'20].
A high-performance C++20 cache simulator with power/area modeling, MESI coherence, prefetching, and multi-level hierarchy support for architecture research and education.
A survey on architectural simulators focused on CPU caches.
Trace-driven cache memory simulator with LRU, MRU, RR and Belady replacement policies.
A graphics tracing and replay framework to explore system-level effects on heterogeneous CPU+GPU memory systems.
This cache simulator is used in order to simulate substitutions in cache using replacement policies (FIFO and LRU) and write back into the cache (using the write-allocate policy).
Simulator of experiments presented in "Enabling Long-term Fairness in Dynamic Resource Allocation", ACM SIGMETRICS 2023.
Computer architecture project : Cache simulator with LRU replacement policy
A Decaying Least Frequently Used Cache implementation.
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