Lightweight and performant dynamic binary translation for RISC–V code on x86–64
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Updated
Mar 29, 2021 - C++
Lightweight and performant dynamic binary translation for RISC–V code on x86–64
JIT-accelerated RISC-V instruction set simulator
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Ratel - a new framework for instruction-level interposition on enclaved applications
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8086–Pentium PC emulator on a dynamic binary translator (AArch64, x86-64): DOS, Windows 3.11, NT 4.0 and Windows 2000 from disk images
Z80 + CP/M dynamic binary translator — 4.3 billion Z80 instructions/sec on Apple Silicon, verified against a lockstep interpreter
Dynamic binary translator from ARM Cortex-M architecture to WebAssembly. University project.
Draft RISC-V H extension for translated x86-64 guests
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