RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and without MDIO interface support
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Updated
Jan 21, 2022 - VHDL
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ethernet-mac
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TinyEMAC, synthesizable 100 Mbit/s Ethernet MAC in VHDL: Wishbone Classic and AXI4-Lite adapters on one shared core, fully verified in GHDL simulation. The Wishbone variant is hardware-proven on FPGA (Cyclone IV, NEORV32) with a lwIP driver.
fpga vhdl rtl lwip ethernet hdl ghdl mii wishbone ip-core network-stack axi4-lite neorv32 ethernet-mac fast-ethernet
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Updated
Oct 11, 2026 - VHDL
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