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AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

simulation vhdl verification vip tlm testbench osvvm simulation-modeling axi4 axi4-lite axi4-stream verification-component

Updated Sep 2, 2026
VHDL

ethanuppal / marlin

Sponsor

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🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl

testing rust hardware simulation verilog testbench verilator

Updated Aug 25, 2026
Rust

cocotb / cocotb-bus

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Pre-packaged testbenching tools and reusable bus interfaces for cocotb

interface bus vhdl verilog hdl testbench cocotb

Updated Aug 31, 2026
Python

Ghonimo / Pre_Silicon-AHB-to_APB-Verification

Star

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

simulation verification vip systemverilog questasim uvm verification-methodologies testbench semiconductor digital-design uvm-verification ahb2apb

Updated Mar 3, 2024
SystemVerilog

brianchiang-tw / leetcode

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A set of practice note, solution, complexity analysis and test bench to leetcode problem set

mysql python go bash golang leetcode solution description implementation testbench complexity-analysis

Updated Jun 16, 2024
Python

ghdl / docker

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Scripts to build and use docker images including GHDL

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Nov 20, 2024
Shell

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

makefile verilog synthesis systemverilog hdl testbench systemverilog-hdl systemverilog-simulation rtl-design systemverilog-test-bench edge-detector-with-mealy

Updated Nov 6, 2022
SystemVerilog

ItzzInfinity / 100-days-of-RTL

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Trying to get a new skill

digital electronics rtl verilog xilinx vivado altera modelsim testbench xilinx-vivado quartus-prime gowin

Updated Dec 31, 2024
Verilog

sumukhathrey / Verilog_ASIC_Design

Star

Verilog for ASIC Design

counter hardware rtl verilog adder testbench gates sequence-detector hardware-modelling

Updated Sep 13, 2021
Verilog

erfnzdeh / verilog-fpga-parking-management-system

Star

Synthesisable Verilog controller for a 700-space university car park: independent occupancy and availability tracking for university and visitor vehicles against one shared capacity, with a transcript-generating testbench and an Intel Quartus project.

fpga rtl verilog icarus-verilog hdl modelsim testbench digital-design quartus sharif sharif-university intel-fpga hardware-design

Updated Aug 12, 2026
Verilog

psychogenic / microcotb

Star

micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop

verification testbench vcd hardware-in-the-loop cocotb

Updated Feb 25, 2025
Python

Suntrakanesh / System-Verilog-bootcamp

Star

System Verilog BootCamp

vhdl verification systemverilog vlsi uvm testbench ovm

Updated Jan 21, 2022
SystemVerilog

daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules

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Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device

spi-interface rtl verilog spi hdl testbench verilog-hdl wishbone spi-master spi-protocol spi-slave verilog-project clock-generator verilog-code verilog-rtl-model wishbone-master

Updated Jul 7, 2024
Verilog

dominiksalvet / super-riscv

Star

Superscalar dual-issue RISC-V processor

open-source pipeline core rtl forwarding systemverilog gtkwave testbench superscalar in-order risc-v microarchitecture low-power verilator ahb3-lite instruction-level-parallelism dual-issue riscv-gcc

Updated Aug 4, 2026
SystemVerilog

dominiksalvet / risc63

Star

Custom 64-bit pipelined RISC processor

Updated Dec 8, 2025
VHDL

gtxzsxxk / veripython

Star

本科编译原理大作业：Verilog to Python Testbench Module：生成 FIRRTL 中间表示的 Verilog 文法子集的前端与基于 Arcilator 生成 Python 仿真模块的后端

python llvm verilog testbench mlir circt

Updated Jan 8, 2025
C++

Hithaishisr / verification-of-apb-based-uart-master-core

Star

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

fpga eda uart systemverilog vlsi uvm testbench digital-design serial-communication apb functional-verification hardware-verification rtl-design rtl-verification uvm-environment

Updated Nov 1, 2025
SystemVerilog

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Here are 347 public repositories matching this topic...

ghdl / ghdl

VUnit / vunit

OSVVM / OSVVM

OSVVM / AXI4

ethanuppal / marlin

cocotb / cocotb-bus

Ghonimo / Pre_Silicon-AHB-to_APB-Verification

brianchiang-tw / leetcode

ghdl / docker

snbk001 / 100DaysofRTL

ItzzInfinity / 100-days-of-RTL

sumukhathrey / Verilog_ASIC_Design

erfnzdeh / verilog-fpga-parking-management-system

psychogenic / microcotb

Suntrakanesh / System-Verilog-bootcamp

daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules

dominiksalvet / super-riscv

dominiksalvet / risc63

gtxzsxxk / veripython

Hithaishisr / verification-of-apb-based-uart-master-core

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