D-TGA correction and D-TGB plan: 64 thought slots, W = thought layer, thought git basics

.claude/board/INTEGRATION_PLANS.md

@@ -1,3 +1,11 @@
+## 2026-10-20 — thought-git-basics-v1 — the basics of thinking with a git API → `.claude/plans/thought-git-basics-v1.md`
+
+**Status:** D-TGB-0..6 PROPOSED, lab, test-first; nothing built. From the ideal state: a slot is taken only at the Rubicon crossing (`Planning → CognitiveWork`) and freed at `Commit` / `Plan` / `Prune`, so no stale branch can exist; squash, prune and GC are kanban outcomes; every thought is replayable from its receipt. `Commit` lands one sparse batch through `LanceCycleWriter`, which gives `KanbanColumn::Commit` its declared-but-missing calcify step. Lance 13 supplies `Ref::Version(branch, version)`, branches, tags, `delta()`, `read_version_transaction`; MemWAL is an optional arm (D-WAL, D-LNC-7). Parent: `thought-git-api-v1.md` correction (#1628).
+
+## 2026-10-20 — thought-git-api-v1 corrected: 64 slots, slot number = CE64 witness pointer
+
+**Status:** DECISION (operator, 2026-10-20). The D-TGA axis is 64 thought slots (0 = main, 1..=63 any thought), not a thought axis beside `AlphaTunnel`'s ten rung lanes; `w_slot` (CE64 bits 53..58) is the slot pointer, so 64 is its width. Pointer rewrite on land and squash, qualified by base version or slot generation. Plan § "Correction: the slot axis and the witness pointer"; entry `2026-10-20-d-tga-slot-axis-witness-pointer.md`.
+
 ## 2026-10-20 — correction: D-RMAP-2 is measured (the 2026-10-19 index line said "not run")
 
 **Status:** CORRECTION. The 2026-10-19 entry lists `d-rmap-2-context-tile-algebra-probe-v1.md` (#1617) as "preregistered GraphBLAS vs BF16 tile probe; not run". Since then §5a measured the polyfill tier (#1623, byte count #1625) and §5a-AMX the AMX tile tier (#1626). The plan is PARTIAL: the `VDPBF16PS`-only tier, tiles above one focus and the GraphBLAS arm are not run. That line is left as written; this entry supersedes it.

.claude/board/STATUS_BOARD.md

@@ -339,7 +339,7 @@ Plan: `.claude/plans/ce64-hypothesis-layers-v1.md`. Plateau: `.claude/knowledge/
 | D-id | scope | status | gate / falsifier |
 |---|---|---|---|
 | **D-HL-0** | Plateau, plan, research map, board entry | Shipped (#1496) | docs only; every claim cites a file or entry |
-| **D-HL-1** | Decisions O1 (46..49), O2 (50..52), O3 (W), O5 (lane budget), O6 (what persists) | Partial: O5 decided 2026-10-14 (up to 64 thought lanes beside the 10 rung lanes); O1 (46..49 = activation i4) and O3 (W = thought layer) decided 2026-10-17; O2, O6 open | stored-meaning changes ship behind a version gate |
+| **D-HL-1** | Decisions O1 (46..49), O2 (50..52), O3 (W), O5 (lane budget), O6 (what persists) | Partial: O5 decided 2026-10-14 (budget: at most 64 thoughts, none required; corrected 2026-10-20: rung is an implied level that can change within a thought, the 10 static rung lanes are deprecated); O1 (46..49 = activation i4) and O3 (W = thought layer) decided 2026-10-17; O2, O6 open | stored-meaning changes ship behind a version gate |
 | **D-HL-2** | Merge-on-read vs in-place revision | Queued | merge-on-read within 1 code of exact on every cell where in-place is not; ≥ 1 cell differs by ≥ 2 codes |
 | **D-HL-3** | Per-delta evidential base as the independence test (layer ≠ source) | Queued | sd ratio within 10 % of 1.0 on all four cases, incl. a cross-layer duplicate (counts once) and two independents in one layer (count twice); a layer-keyed rule must fail those two |
 | **D-HL-4** | Narsese parallel calibration (OpenNARS vs CE64 deltas, `jc::reliability`) | Queued (after D-HL-2 and D-HL-3) | an encoding that does not beat linear ICC by the pre-declared margin is dropped |
@@ -348,12 +348,19 @@ Plan: `.claude/plans/ce64-hypothesis-layers-v1.md`. Plateau: `.claude/knowledge/
 | **D-HL-7** | SparseDelta record through the split-tunnel append | Queued | replay composite = in-memory composite; dropping one delta changes only its rows |
 | **D-HL-8** | Validation ladder: when a layer may commit | Queued | some rung beats "commit everything" on oracle agreement, with a no-meta control |
 | **D-TGA-0** | Thought git API: pre-registration (fixtures, from-scratch oracle, disables) — `.claude/plans/thought-git-api-v1.md` | Queued | written before any code |
-| **D-TGA-1** | Thought type, branch/discard/write/diff, 63-branch limit (64 thoughts with main), givens refusal | Queued | 63rd branch accepted, 64th refused, slot 0 never handed out; a new value on a given records a contradiction and changes nothing |
+| **D-TGA-1** | Thought type, branch/discard/write/diff, 63-branch limit (64 thoughts with main), givens refusal | Queued | 63rd branch accepted, 64th refused, slot 0 never handed out; a new value on a given records a contradiction and changes nothing; after `land` no live edge carries the landed slot; an edge from a recycled slot's old generation is refused (scope: replaces the ten rung lanes, plan § "Correction: the slot axis", 2026-10-20) |
 | **D-TGA-2** | Read plane R and status | Queued | a read outside R is never reported stale |
 | **D-TGA-3** | rebase (four masks, no data moved) | Queued | rebase-then-squash == from-scratch re-run on v+1, including a deletion in main (retract then re-derive); disables: no stale re-run, no conflict check, no retraction |
 | **D-TGA-4** | land through the revision gate into the next Lance version (D-HL-8) | Queued | landing a thought that is behind is refused |
 | **D-TGA-5** | squash_into (partial squash) and blame | Queued | blame returns original sources after slot reuse |
 | **D-TGA-6** | MergeQueue | Queued | independent thoughts == landed by hand in FIFO order; a thought reading another negated lands after it; a cycle through negation refused at enqueue |
+| **D-TGB-0** | thought git basics: fixtures per Rubicon outcome, `w_slot` reference fixtures, from-scratch oracle (`thought-git-basics-v1.md`) | Queued (lab) | disables written before code |
+| **D-TGB-1** | slot pool on the Rubicon crossing: slot taken at `Planning → CognitiveWork`, freed at `Commit`/`Plan`/`Prune` | Queued (lab) | no slot without a live card (no stale branch); crossing refused at 63 taken |
+| **D-TGB-2** | `w_slot` lane labels (W = thought layer, not a pointer) qualified by base version / slot generation | Queued (lab) | no live cell carries a landed slot; old-generation edge refused |
+| **D-TGB-3** | `Commit` lands one sparse batch through `LanceCycleWriter`; `DurableRef` = dataset + `Ref::Version(branch, version)` | Queued (lab) | empty cycle writes nothing; re-submit reconciles; two branches at version 7 told apart |
+| **D-TGB-4** | receipt (base ref, program id, seeds, slot generation) instead of history | Queued (lab) | replay from receipt reproduces writes cell for cell |
+| **D-TGB-5** | reads as resident folds: `checkout`/`log`/`diff`/`blame` | Queued (lab) | equal the oracle; durable `diff` equals Lance `delta()` |
+| **D-TGB-6** | MemWAL `Commit` arm behind a switch, reads stay resident | Queued; waits on D-LNC-7 | enabled only past the D-WAL crossover |
 | **D-HL-9** | Hydration budget split sweep | Queued | agreement not flat in k |
 | **D-HL-10** | NAL inference ISA: `ogar-nal` loco vocabulary + mask-risc dialect (a vocabulary on the existing IR, ledger R18); detailed as D-NALP | Queued (design; after D-HL-4) | per-op parity with the CE64 register method of the same name; agreement with OpenNARS within D-HL-4's tolerance; no second IR |
 

.claude/board/entries/2026-10-20-ce64-isa-not-storage.md

@@ -0,0 +1,11 @@
+# 2026-10-20 — CE64 is an ISA contract: thought-aware in the hot path, arbitrary after a seal
+
+**Status:** DECISION (operator, 2026-10-20). **Basis:** the operator's words: "Causaledge64 is an Isa contract / Not a storage contract / so when causaledge64 is having meta awareness in hot path it is thought aware / If it's lowered into lance seal, the in ram reference becomes arbitrary / The thinking styles used and eventually the reasoning replay should rather live in the thinking, or be linked with the kanban lane versions".
+
+- Closes capstone §8 row 4 ("CE64 is not storage" vs "the result lives in 59..63"): both hold, in different places. In the hot path, inside a live thought, W names the lane and 59..63 carries the result. In a sealed Lance version W is arbitrary, because slot numbers recycle.
+- Persisting CE64 does not make it a storage format: like BF16 written to disk, the bits are kept bit-exact and keep their ISA meaning; storage is the container, not the contract. Only a field whose referent exists at run time loses its meaning in a sealed copy: W, the slot number of a live thought (as a TCP port in a saved pcap still names a connection that is gone). (operator clarification, same day: "It's like TCP IP BF16 bit exact mantissa / if you save BF16 to Disk it's also ISA even if it's used in storage?")
+- Extends entry 2026-10-17-ce64-one-layout D1 ("CE64 is not storage") to the seal boundary.
+- Thinking styles used and the reasoning replay live in the thought (program or template id) or link to the kanban lane's Lance versions, never in sealed CE64 bits.
+- Applied in `thought-git-api-v1.md` (correction item 7), `thought-git-basics-v1.md` (D-TGB-3, D-TGB-4), and the capstone (§8 row 4, field table row 53..58).
+
+OPEN: which of the two homes (in the thought, or linked to the kanban lane version) a landed receipt uses; D-TGB-4 measures replay either way.

.claude/board/entries/2026-10-20-d-tga-slot-axis-witness-pointer.md

@@ -0,0 +1,19 @@
+# 2026-10-20 — D-TGA-SLOT-AXIS — thoughts are 64 slots, and the slot number is CE64's witness pointer
+
+**Status:** DECISION (operator, 2026-10-20). **Basis:** VERIFIED-IN-CODE (`causal-edge/src/layout.rs`, const `W_SHIFT`, value 53; 6-bit `CausalEdge64::w_slot`).
+
+- Thinking with a git API, at the cost of a sparse write and a merge on read.
+- The axis is 64 dynamically allocated thought slots: 0 is main (the merged state the frame starts from), 1..=63 are any thought. Rung is a claim attribute, not an axis; `alpha_tunnel.rs`'s ten rung lanes are superseded. This closes the "10 rung lanes, not a 64-lane budget" conflict in `2026-10-12-ce64-hypothesis-layers-plateau.md`.
+- 64 is the width of CE64 bits 53..58: a thought's slot number travels in every causal edge, so thoughts can reference each other.
+- At the ceiling a new thought requires squash or land, never a 65th slot. `land` rewrites pointers to the landed slot to 0; `squash_into` rewrites them to the surviving slot; every pointer is qualified by the frame's base version (0) or the slot's generation (1..=63); `ThoughtCommitId` is never reused.
+- Written into `thought-git-api-v1.md` § "Correction: the slot axis and the witness pointer", with two new D-TGA-1 falsifiers.
+
+- Squash-or-land follows from the pointer graph (WORKING-MODEL): reference count per slot is one fold over `w_slot`; land in topological order; a cycle squashes into one slot first; conflicts propagate to dependants; the same graph orders `MergeQueue`.
+
+OPEN: measuring that policy; the `edge.rs` "0 = no corpus anchor" doc line, to correct with D-TGA-1.
+
+Correction (2026-10-20, review #1628): two readings of bits 53..58 exist in code. `deepnsm-v2/src/wire.rs` follows `w_slot` as a witness pointer that ends at 0; `MailboxSoA::apply_edges` filters on it as the mailbox's corpus and has no production caller. Which reading owns the bits is OPEN (operator); the pointer-graph policy assumes the witness reading.
+
+Correction (2026-10-20, operator): the reading is not open. W = thought layer 0..63 was decided on 2026-10-17 (#1597, epistemic-frontier capstone; 0 givens = main, 1..63 hypotheses). The mailbox corpus filter and `deepnsm-v2`'s `WitnessTable` index are competing readers to migrate (capstone §8 row 2), not candidate readings. The "operator decision OPEN" line above is struck.
+
+Correction (2026-10-20, operator): W is not a pointer between thoughts. It names the lane the state belongs to and points nowhere (capstone § "Why presence bits replace references"; 2026-10-17 clicks entry). The pointer-graph WORKING-MODEL above (reference count over `w_slot`, topological land order, cycle squash, conflict propagation) is withdrawn; squash-or-land is OPEN and must read the deltas' source bitsets (D-HL-3) and the written-by words. The "thoughts can reference each other" line above is withdrawn with it.

.claude/board/entries/2026-10-20-d-tgb-thought-git-basics.md

@@ -0,0 +1,16 @@
+# 2026-10-20 — D-TGB — thought git basics planned from the ideal state
+
+**Status:** PROPOSED, lab. **Basis:** VERIFIED-IN-CODE for the lifecycle (`lance-graph-contract/src/kanban.rs`, `KanbanColumn::next_phases`) and for the Lance surface (`lance-13.0.0` sources: `refs::Ref`, `create_branch`, `delta`, `read_version_transaction`, `cleanup_old_versions`, `mem_wal`); MEASURED for MemWAL (`2026-10-15-d-wal-shootout.md`).
+
+- Thinking with a git API, at the cost of a sparse write and a merge on read.
+- A slot is taken only at the Rubicon crossing and freed at `Commit` / `Plan` / `Prune`: no stale branch can exist, and squash, prune and GC are kanban outcomes, not a background job.
+- `Commit` lands one sparse batch through `LanceCycleWriter`; `KanbanColumn::Commit`'s calcify step is declared only today.
+- `DurableRef` = dataset + Lance's own global `Ref::Version(branch, version)`. Lance branches are two-phase and can leave zombies, so they are for long-lived experiments, not one per thought.
+- Receipts make discarding safe: a replay from (base ref, program id, seeds, slot generation) must reproduce the writes.
+- MemWAL is an optional `Commit` arm past the D-WAL crossover; reads stay resident folds.
+
+OPEN: card granularity (mailbox card or per-move card); the PR entry under MemWAL; Datalog awareness later.
+
+Correction (2026-10-20, review #1628): `LanceCycleWriter` commits one batch per supervisor cycle, so every `Commit` in a cycle coalesces into one batch and one version; a landed thought is (version, thought id within the batch). D-TGB-2 is blocked on the `w_slot` reading decision.
+
+Correction (2026-10-20, operator): D-TGB-2 is not blocked. W = thought layer 0..63 is the 2026-10-17 decision (#1597); D-TGB-2 carries the migration of the competing readers (`MailboxSoA::apply_edges`, `deepnsm-v2`'s `WitnessTable` index).

.claude/board/entries/README.md

@@ -25,19 +25,22 @@ index row, (3) no duplicate entry id. Checks 1 and 2 are deliberately
 opposite directions; the stranding this convention prevents shows up in
 exactly one of them, never both.
 
-383 entries, 2026-08-06 .. 2026-10-20.
+386 entries, 2026-08-06 .. 2026-10-20.
 
 | date | entry id | finding | file |
 |---|---|---|---|
 | 2026-10-20 | `relstore-quack-petgraph-plan` |  | [2026-10-20-relstore-quack-petgraph-plan.md](2026-10-20-relstore-quack-petgraph-plan.md) |
 | 2026-10-20 | `D-RST` |  | [2026-10-20-relstore-geometry-not-graph-api.md](2026-10-20-relstore-geometry-not-graph-api.md) |
 | 2026-10-20 | `recursive-perspective-rebinding` |  | [2026-10-20-recursive-perspective-rebinding.md](2026-10-20-recursive-perspective-rebinding.md) |
 | 2026-10-20 | `prs-1601-1617-plan-links` |  | [2026-10-20-prs-1601-1617-plan-links.md](2026-10-20-prs-1601-1617-plan-links.md) |
+| 2026-10-20 | `D-TGB` | thought git basics planned from the ideal state | [2026-10-20-d-tgb-thought-git-basics.md](2026-10-20-d-tgb-thought-git-basics.md) |
+| 2026-10-20 | `D-TGA-SLOT-AXIS` | thoughts are 64 slots, and the slot number is CE64's witness pointer | [2026-10-20-d-tga-slot-axis-witness-pointer.md](2026-10-20-d-tga-slot-axis-witness-pointer.md) |
 | 2026-10-20 | `D-RPR` |  | [2026-10-20-d-rpr-consolidation-1624.md](2026-10-20-d-rpr-consolidation-1624.md) |
 | 2026-10-20 | `D-RPR-1` |  | [2026-10-20-d-rpr-1-handoff-lab-demo.md](2026-10-20-d-rpr-1-handoff-lab-demo.md) |
 | 2026-10-20 | `D-RMAP-2` |  | [2026-10-20-d-rmap-2-tile-gemm-cell.md](2026-10-20-d-rmap-2-tile-gemm-cell.md) |
 | 2026-10-20 | `D-RMAP-2-AMX` |  | [2026-10-20-d-rmap-2-amx-tier.md](2026-10-20-d-rmap-2-amx-tier.md) |
 | 2026-10-20 | `D-RMAP-2-AMX-RERUN` | §5a-AMX re-measured on a second AMX host | [2026-10-20-d-rmap-2-amx-remeasured.md](2026-10-20-d-rmap-2-amx-remeasured.md) |
+| 2026-10-20 | `ce64-isa-not-storage` |  | [2026-10-20-ce64-isa-not-storage.md](2026-10-20-ce64-isa-not-storage.md) |
 | 2026-10-19 | `post-merge-recovery-1601-1617` |  | [2026-10-19-post-merge-recovery-1601-1617.md](2026-10-19-post-merge-recovery-1601-1617.md) |
 | 2026-10-19 | `native-join-relationship-table` |  | [2026-10-19-native-join-relationship-table.md](2026-10-19-native-join-relationship-table.md) |
 | 2026-10-19 | `mork-pathmap-schnellverschluss` |  | [2026-10-19-mork-pathmap-schnellverschluss.md](2026-10-19-mork-pathmap-schnellverschluss.md) |