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fix: the selection trace reads the diagram left to right - #114
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…ake's ready wires do not cut it short Selecting a node in a netlist lit only its two neighbours: every `ready` wire runs against the data it answers, so by the arrows alone every two connected nodes form a cycle, and on a cycle the trace was cut to the direct neighbours. Now the walk follows each wire the way the diagram is read: a wire drawn back to the left (a ready, a loop's feedback) is walked against its arrow, so a laid-out diagram is a DAG and the trace follows the data as far as it goes, upstream to the left and downstream to the right. A port reached that way is walked on from too, since it has wires of its own. A model with no positions, and a cycle that remains, behave as before. On the mul_mul module of a 1597-module netlist, selecting addi73 traces 141 elements upstream where it traced four. Claude-Session: https://claude.ai/code/session_01EToj6RJRMSSHQiqGNMU9wv
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Selecting a node in a SystemVerilog netlist lit only its two neighbours (reported on
netlist__Netlist__0.v, insideCore_wrapper / core_wrapped / instance52). Every handshakereadywire runs against the data it answers, so by the arrows alone every two connected nodes form a cycle, and on a cycle the trace was cut to the direct neighbours.The walk now follows each wire the way the diagram is read, left to right: a wire drawn back to the left (a
ready, a loop's feedback) is walked against its arrow. A laid-out diagram is then a DAG, and the trace follows the data as far as it goes: upstream to the left, downstream to the right. A port reached that way is walked on from too. A model without positions, and a cycle that remains, behave as before.Checked headlessly on the netlist's
mul_mul_Bbehavioralmodule (107 nodes, 218 edges): selectingaddi73now traces the path back to the module inputs, 141 elements upstream, where it traced four. Two new unit tests pin the handshake chain and a loop drawn left to right.https://claude.ai/code/session_01EToj6RJRMSSHQiqGNMU9wv