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Release 0.7.10 - #703
Release 0.7.10#703
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| "it ne", | ||
| "bxne lr", | ||
| "cpsie i", | ||
| "isb", |
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I don't think we need ISB here - CPSIE is self synchronising. The only reason to add one would be to ensure any pending interrupts run before the next instruction, but I don't think that matters here.
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I understand CPSID is self synchronising but CPSIE is not. Not sure if what synchronisation CPSIE has is sufficient to apply the effects of the MSR or not (or perhaps we should move the ISB to immediately after MSR?).
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Ah. Hmm.
I guess the failure mode here is that the next instruction might run before being preempted by a pending exception. That feels OK? The Arm doc does note that CPSIE followed by CPSIE is ok (interrupts will run in the gap between the two).
I think putting the ISB after the MSR makes more sense.
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Agreed, I've pushed to move the ISB to just after MSR instead.
| "it ne", | ||
| "bxne lr", | ||
| "cpsie i", | ||
| "isb", |
There was a problem hiding this comment.
I don't think we need ISB here - CPSIE is self synchronising. The only reason to add one would be to ensure any pending interrupts run before the next instruction, but I don't think that matters here.
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Releases fixes for #702 and #697.