[atomchild411]

irq: an InterruptController trait, with the Indy and Indigo2 interrupts on it

Each Indy/Indigo2 device that raises an interrupt had its own callback trait or held the whole Ioc to set one line. This adds src/irq.rs, one shape for every interrupt, and moves IP22/IP24/IP28 onto it. As discussed, it is the base for the O2: its CRIME and MACE controllers will implement the same trait, so devices see one interface on every machine.

The trait

pub trait InterruptController: Send + Sync {
    fn set_line(&self, line: u32, level: bool);
}
pub struct IrqLine { /* controller + input */ }   // IrqLine::set(level)

A device holds an IrqLine and drives it to its level. The controller decides what the level means: a status bit behind a mask, an input ORed with others, or a cascade further up.

The changes, one device per commit

• IOC is a controller. Each IocInterrupt is a line, numbered in declaration order; Ioc::irq_line(source) hands one out. set_interrupt runs the same code as before (now IocState::set_source).
• HPC3 INTSTAT is a controller: a line per INTSTAT bit. A SCSI channel's chip and DMA bits are ORed onto its IOC line. A chip-INT ack still settles the paired PDMA half, as Hpc3Irq did. The SEEQ's level still goes to Ethernet on its own, not ORed with the Ethernet DMA bits.
• These now hold IrqLines: the Z85C30, the 8042, VINO, both WD33C93As and their PDMA channels, the SEEQ, the MC's GIO DMA engine, Ultra64, MGRAS (FIFO, general and retrace) and REX3 (VV_INT_N, FIFO_INT_N).
• Gone: IrqCallback, Ps2Callback, VinoIrq, ScsiCallback, SeeqCallback, PdmaCallback, the REX3 vblank/FIFO closures, and the IocIrqLine, Hpc3Irq, EnetSeeqIrq and VinoIrqAdapter adapters.
• The machine now hands MGRAS and REX3 the IOC lines their slot is wired to, instead of each device picking its own sources.
• Constructors that took a callback or the Ioc now take the line(s): Z85c30::new*, Ps2Controller::new, Wd33c93a::new*, Seeq8003::new/with_config, Ultra64::new, Mgras::new; MemoryController::set_ioc is now set_dma_irq, and REX3's setters are set_vblank_irq/set_fifo_full_irq. REX3's field names are unchanged, since docs and the lock diagnostics use them.

Behaviour is meant to be identical: the same bits, the same ORs, the same lock order. Left as they are, because they are not plain levels: the 8254 timers (latched, cleared by TMR_CLR), GR2's retrace (a rising edge acked IOC-side, plus the EXT_IO status), and the IOC's output to the CPU's Cause bits.

Tests

• New unit tests: every IOC source is a line, driving what set_interrupt drives; INTSTAT ORs a SCSI channel's halves, a chip ack settles the DMA half, and the SEEQ's level reaches Ethernet as it is; the 8042's line follows its receive queue; the SCC test now uses the shared LevelProbe.
• cargo test --lib: all pass, apart from breakpoints_can_be_set_while_running_and_report_their_hit and udp_fragmented_both_ways, which fail the same way on main here.
• Built in the three CI configurations.
• Booted windowed (with the ps2 PR) on every graphics board each machine takes. On each one: hinv, a disk read, the CD (mediad), audio playback, ping to the gateway, X, a keyboard login to the desktop, and a clean shutdown.

Machine	Boards	Result
Indy (IP24, R4400)	Newport, dual-head Newport, XZ	pass
Indigo2 IP22 (R4400)	Newport, XZ, Extreme	pass
Indigo2 IP28 (R10000)	Solid, High, Max IMPACT	pass
Indigo2 IP22 (R4400)	Solid, High, Max IMPACT	PROM panic, identical on main (see below)

Extreme's desktop and the dual-head Indy's head 0 were also compared with main pixel by pixel: identical.

The IP22 IMPACT rows: with Solid, High or Max IMPACT on an R4400 Indigo2, the PROM prints "NVRAM checksum is incorrect: reinitializing" and then takes a UTLB miss at 0x10c (EPC 0x9fc36988), before IRIX loads. main does exactly the same with the same disk and NVRAM, so those three couldn't be tested here. The same install booted on IMPACT on 2026-10-01.

Found on the way, not changed here

These are behaviour this PR keeps as it was, filed as issues:

• Shared GIO interrupt bits have no wired-OR: two heads or slots set and clear the same L0/L1 bit, so one can drop the other's interrupt (Shared GIO interrupt bits have no wired-OR between heads/slots #262).
• Ultra64's three sources share GioExp0 with no OR: acking one drops the line while another may be pending (Ultra64: three sources share GioExp0 with no OR; one ack can drop another's interrupt #263).
• Ioc::power_on stores 0 to the CPU's whole interrupt word, which also clears IP7 (the CPU timer) (Ioc::power_on clears the CPU's whole interrupt word, including IP7 (CPU timer) #264).

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