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RISC-Processor

Ecolash / RISC-Processor

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𝗠𝗶𝗻𝗶𝗠𝗜𝗣𝗦 | 𝗥𝗜𝗦𝗖 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗗𝗲𝘀𝗶𝗴𝗻 | 𝗖𝗦𝟯𝟵𝟬𝟬𝟭 𝗖𝗼𝘂𝗿𝘀𝗲 𝗣𝗿𝗼𝗷𝗲𝗰𝘁

pipeline processor assembler vivado assembly-language-programming computer-architecture verilog-hdl instruction-set-architecture mips-architecture iitkgp control-unit fpga-programming controlpath computer-organization-and-design risc-architecture datapath-design
  • Updated Sep 14, 2025
  • Verilog

shahed22 / Architectural-Design-for-Bus-interface-connected-with-LFSR

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bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

asic fsm interface architecture rtl verilog peripherals datapath soc testbench lfsr 32-bit 32bit bus-interface asic-design controlpath datapath-design lfsr-algorithm
  • Updated May 28, 2024
  • Verilog

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