4-bit Serial Adder/Subtractor with Parallel Load
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Updated
Nov 7, 2020 - VHDL
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serial-adder
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Structural and behavioral VHDL digital design in Quartus: a from-scratch serial adder with gate-level propagation delays, a 74LS194A-style bidirectional shift register, and Moore FSMs implemented both ways, with testbenches and simulation waveforms.
fpga simulation vhdl rtl finite-state-machine testbench shift-register digital-design quartus moore-machine serial-adder
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Updated
Sep 9, 2026 - VHDL
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